TAM, controller, selector, scan router, external data and control buses
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
1. An integrated circuit test architecture comprising:
(a) cores of functional circuits;
(b) test wrapper architectures, each test wrapper architecture being connected with one core;
(c) test access mechanisms, each test access mechanisms being connected with one of the test wrapper architectures;
(d) test access mechanism controllers having test access mechanism interface buses, each interface bus being connected with one of the test access mechanisms;
(e) an externally accessible data input bus connected with the test access mechanism controllers and the test access mechanisms; and
(f) an externally accessible control bus connected with the test access mechanism controllers, the control bus including a wrapper clock lead, a select wrapper instruction register lead, a shift wrapper lead, a capture wrapper lead, an update wrapper lead, a transfer wrapper lead, and a wrapper reset lead.
2. An integrated circuit test architecture comprising:
(a) cores of functional circuits;
(b) test wrapper architectures, each test wrapper architecture being connected with one core;
(c) test access mechanisms, each test access mechanisms being connected with one of the test wrapper architectures;
(d) test access mechanism controllers having test access mechanism interface buses, each interface bus being connected with one of the test access mechanisms;
(e) an externally accessible data input bus connected with the test access mechanism controllers and the test access mechanisms; and
(f) an externally accessible control bus connected with the test access mechanism controllers;
(g) in which each wrapper architecture includes:
(i) a wrapper control interface having a wrapper clock input, a select wrapper instruction register input, a shift wrapper input, a capture wrapper input, an update wrapper input, a transfer wrapper input, a wrapper reset input, and control outputs;
(ii) a wrapper serial input and a wrapper serial output;
(iii) a wrapper instruction register connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs;
(iv) a wrapper bypass register connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs;
(v) wrapper boundary registers connected to inputs and outputs of the functional circuits, connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs; and
(vi) data register scan paths connected to the functional circuits, connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs.