IP Library Granted Patent US 9,607,861
Granted Patent B2
US 9,607,861 · App. 15/016,070 · Granted Mar 28, 2017

Semiconductor device and method of manufacturing the same

Inventors: Junji Shiota (Hamura, JP); Ichiro Kono (Higashiyamato, JP)
Assignee: AOI ELECTRONICS CO., LTD.
H01L21/56H01L21/304H01L21/3081H01L21/30625H01L21/6835H01L21/6836H01L21/768H01L21/78H01L23/3114H01L23/562H01L24/11H01L24/12H01L23/525H01L29/0657H01L2221/6834H01L2221/68327H01L2221/68381H01L2224/94
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Quick Facts
Patent No.
US 9,607,861
App. No.
15/016,070
Granted
Mar 28, 2017
Kind
B2
Abstract

A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Claims (32)

1. A method of manufacturing a semiconductor device, comprising steps of:

(a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon;

(b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face;

(c) dividing the wafer into multiple chip bodies concurrently with or after step (b);

(d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and

(e) removing the support plate after step (d).

2. A method of manufacturing a semiconductor device, comprising steps of:

(a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon;

(b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face;

(c) bonding multiple reinforcing layers to the second main face of the wafer so as to be arrayed along the second main face of the wafer after step (b);

(d) dividing the wafer into multiple chip bodies after step (c) so that the chip bodies correspond to the respective reinforcing layers; and

(e) removing the support plate after step (d).

3. The method of manufacturing a semiconductor device according to claim 2 , wherein, in step (d), the wafer is etched through the multiple reinforcing layers functioning as a mask.

4. A method of manufacturing a semiconductor device, comprising steps of:

(a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon;

(b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face;

(c) bonding a reinforcing plate to the second main face after step (b);

(d) dividing the reinforcing plate to multiple reinforcing layers and dividing the wafer into multiple chip bodies so that the chip bodies correspond to the respective reinforcing layers after step (c); and

(e) removing the support plate after step (d).

5. The method of manufacturing a semiconductor device according to claim 4 , wherein, in step (d), after the dividing of the reinforcing plate, the wafer is divided into the multiple chip bodies by etching the wafer through the multiple reinforcing layers functioning as a mask.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein a thermosetting resin film is formed on the first main face of the wafer to cover a rewiring layer formed on the wafer so that the rewiring layer is in a direct contact with the thermosetting resin film.

7. The method of manufacturing a semiconductor device according to claim 1 , wherein a rigidity of a reinforcing layer is higher than a rigidity of the wafer having a thickness corresponding to a total thickness of the reinforcing layer and a bonding layer, the bonding layer bonding the reinforcing layer to the wafer.

8. A method of manufacturing a semiconductor device, comprising steps of:

(a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit and a thermosetting resin layer covering the integrated circuit which are disposed on the first main face;

(b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face;

(c) applying a thermosetting resin to the second main face of the wafer and curing the thermosetting resin after step (b) to form a cured shrinkage layer having a higher internal stress than an internal stress of the thermosetting resin layer;

(d) dividing the wafer into multiple chip bodies after step (c); and

(e) removing the support plate after step (d).

9. The method of manufacturing a semiconductor device according to claim 8 , wherein a rewiring layer formed on the wafer is covered by the thermosetting resin layer so that the rewiring layer is in a direct contact with the thermosetting resin layer.

10. The method of manufacturing a semiconductor device according to claim 8 , wherein

in step (c), the cured shrinkage layer is patterned into a grid along the second main face of the wafer, and

the wafer is divided into multiple chip bodies so that the chip bodies correspond to respective cured shrinkage layers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2016
From: TERA PROBE, INC.
To: AOI ELECTRONICS CO., LTD.
Reel/Frame 040371/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: SHIOTA, JUNJI; KONO, ICHIRO
To: TERA PROBE, INC.
Reel/Frame 037669/0484 →
Priority Claims (1)
JP 2015-022191 · Feb 6, 2015 · national
Continuity (1)
Related Publication 20160233111A1 · Aug 11, 2016