IP Library Patent Application 15016612
Patent Application
App. No. 15/016,612

EPITAXIALLY GROWN SILICON GERMANIUM CHANNEL FINFET WITH SILICON UNDERLAYER

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Quick Facts
Patent No.
US None
App. No.
15/016,612
Abstract

Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Claims (11)

1 . A semiconductor structure comprising:

a channel layer disposed on a semiconductor substrate, wherein the semiconductor substrate comprises at least an underlayer;

a plurality of fins patterned in the channel layer and the underlayer, wherein a first set of the plurality of fins are in an NFET region and a second set of the plurality of fins are in a PFET region;

a gate structure and a set of spacers, wherein a portion of the gate structure and the set of spacers are disposed around the plurality of fins; and

a source drain region formed adjacent to the gate structure, wherein a source drain material is present in the source drain region.

2 . The semiconductor structure of claim 1 , wherein the underlayer comprises Si, and wherein the underlayer has a thickness that is greater than or equal to 5 nm and less than or equal to 10 nm.

3 . The semiconductor structure of claim 1 , wherein the channel layer comprises at least one of: Si, SiGe, and III-V a material.

4 . The semiconductor structure of claim 11 , wherein the set of spacers are configured to be undercut.

5 . The semiconductor structure of claim 11 , wherein the source drain material comprises SiGe, and wherein the SiGe has a concentration that is greater than or equal to 30% Ge and less than or equal to 60% Ge.

6 . The semiconductor structure of claim 1 , wherein the underlayer comprises Si and less than 1% carbon. The semiconductor structure of claim 1 , wherein the channel layer comprises SiGe, and wherein the SiGe has a density that is greater than or equal to 20% Ge and less than or equal to 50% Ge.

8 . The semiconductor structure of claim 1 , wherein the channel layer has a thickness that is greater than or equal to 30 nm and less than or equal to 100 nm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: GLOBALFOUNDRIES INC.
To: ALSEPHINA INNOVATIONS INC.
Reel/Frame 049709/0871 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2016
From: CHENG, KANGGUO; HARLEY, ERIC C.T.; HOLT, JUDSON R.; KARVE, GAURI V.; KE, YUE; LIU, DERRICK; MCARDLE, TIMOTHY J.; MOCHIZUKI, SHOGO; REZNICEK, ALEXANDER; SMITH, MELISSA A.
To: GLOBALFOUNDRIES INC.
Reel/Frame 037677/0627 →