RF SOI switch with backside cavity and the method to form it
View Patent ↗An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.
1. A method of manufacturing an integrated circuit, the method comprising:
providing a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer;
forming a protective layer on the second semiconductor substrate;
forming a plurality of shallow trench isolations through the protective layer and the second semiconductor substrate;
forming a plurality of via holes through the shallow trench isolations and the insulating layer, the via holes extending into a portion of the first semiconductor substrate;
selectively removing a portion of the first semiconductor substrate disposed between the via holes to form a continuous cavity area;
filling the via holes with a dielectric material and performing a chemical mechanical polishing process to remove excess of the dielectric material to form a plurality of isolation plugs dividing the continuous cavity area into a plurality of separate cavities;
removing a portion of the shallow trench isolations and a portion of the isolation plugs higher than the second semiconductor substrate and the protective layer; and
forming a transistor within a portion of the second semiconductor substrate disposed between two adjacent shallow trench isolations.
2. The method of claim 1 , wherein selectively removing the portion of the first semiconductor substrate comprises a wet etching with an aqueous solution of TMAH, KOH, or NH3-H2O.
3. The method of claim 1 , wherein the first semiconductor substrate is a silicon layer having a plane orientation (111), and the second semiconductor substrate is a silicon layer having a plane orientation (111).
4. The method of claim 1 , wherein the extended portion of a via hole into the first semiconductor substrate has a depth greater than 100 nm.
5. The method of claim 1 , further comprising, after forming the transistor, forming a dielectric layer on the transistor.