Control circuit for power converter
A circuit for controlling a first field-effect transistor of a power converter, intended for a converter including at least one first and one second transistor connected in series between two terminals for applying a first voltage, the circuit including a circuit for detecting the opening of the second transistor.
1. A circuit for controlling a first field effect transistor of a power converter, intended for a converter comprising at least a first and a second field effect transistor series-connected between two terminals of application of a first voltage, the circuit comprising:
an output terminal intended to be connected to the gate of the first field effect transistor;
an input terminal intended to be connected to the source of the first field effect transistor;
two control transistors series-connected between two terminals of application, respectively, of a first power supply voltage which is positive or zero with respect to the potential present on the input terminal and of a second power supply voltage which is negative or zero with respect to the potential of the input terminal, wherein the junction point of the two series-connected control transistors is connected to the gate of the first field effect transistor;
a control terminal intended to receive a control signal for controlling the turning on or off of the first field effect transistor;
a detection circuit for detecting a variation of the drain-source voltage due to the turning-off of the second field effect transistor, wherein the detection circuit is connected to the gate of the first field effect transistor and detects a variation of the gate current or of the gate-source voltage of the first field effect transistor when the control circuit is in a first operating mode, called monitoring mode, in which the two control transistors are off, placing the gate of the first field effect transistor in a high-impedance state; and
a logic block for combining the control signal and at least one signal supplied by the detection circuit to control the turning on or off of each of the control transistors.
2. The circuit of claim 1 , wherein the detection circuit is powered between the two terminals of application of the first and second power supply voltages.
3. The circuit of claim 1 , wherein the detection circuit comprises at least one stage comprising a current mirror formed of two MOS having a transistor having its source connected to a terminal of application of the second power supply voltage, the other transistor having its source connected to the output terminal of the control circuit.
4. A power converter, comprising:
at least a first and a second field effect transistor series-connected between two terminals of application of a first voltage; and
a circuit configured to control the first field effect transistor, comprising:
an output terminal intended to be connected to the gate of the first field effect transistor;
an input terminal intended to be connected to the source of the first field effect transistor;
two control transistors series-connected between two terminals of application, respectively, of a first power supply voltage which is positive or zero with respect to the potential present on the input terminal and of a second power supply voltage which is negative or zero with respect to the potential of the input terminal, wherein the junction point of the two series-connected control transistors is connected to the gate of the first field effect transistor;
a control terminal intended to receive a control signal for controlling the turning on or off of the first field effect transistor;
a detection circuit for detecting a variation of the drain-source voltage due to the turning-off of the second field effect transistor, wherein the detection circuit is connected to the gate of the first field effect transistor and detects a variation of the gate current or of the gate-source voltage of the first field effect transistor when the control circuit is in a first operating mode, called monitoring mode, in which the two control transistors are off, placing the gate of the first field effect transistor in a high-impedance state; and
a logic block for combining the control signal and at least one signal supplied by the detection circuit to control the turning on or off of each of the control transistors.
5. The power converter of claim 4 , wherein the input terminal of the circuit is connected to one of the terminals of application of the first voltage.
6. The power converter of claim 5 , further comprising a second circuit configured to control the second field effect transistor, wherein an input terminal of the second circuit is connected to a junction point between the first and second field effect transistors.
7. The power converter of claim 4 , wherein the detection circuit is powered between the two terminals of application of the first and second power supply voltages.
8. The power converter of claim 4 , wherein the detection circuit comprises at least one stage comprising a current mirror formed of two MOS having a transistor having its source connected to a terminal of application of the second power supply voltage, the other transistor having its source connected to the output terminal of the control circuit.