IP Library Granted Patent US 10,073,725
Granted Patent B2
US 10,073,725 · App. 15/041,207 · Granted Sep 11, 2018

Distributed input/output virtualization

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Quick Facts
Patent No.
US 10,073,725
App. No.
15/041,207
Granted
Sep 11, 2018
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (DVC) disposed on the host computing device, and a virtualized input/output (I/O) device in communication with the DVC.

Claims (46)

1. An apparatus, comprising:

a host computing device;

a distributed virtualization controller (DVC) comprising circuitry physically disposed on the host computing device; and

a virtualized input/output (I/O) device in communication with the DVC, wherein the virtualized I/O device is configured to share resources of the virtualized I/O device between the host computing device and another host computing device coupled to the virtualized I/O device and wherein the DVC is configured to virtualize the I/O device to the host computing device on which the DVC is physically disposed.

2. The apparatus of claim 1 , further comprising a management host computing device including a DVC disposed thereon, wherein the management host computing device is in communication with a network switch.

3. The apparatus of claim 2 , wherein the management host computing device is configured to initiate a recovery mechanism on a physical I/O device in communication with the DVC in response to an error condition.

4. The apparatus of claim 1 , wherein the DVC is configured to expose at least one queue to the host computing device.

5. The apparatus of claim 4 , wherein the at least one queue is part of a multi-queue interface.

6. The apparatus of claim 4 , wherein the at least one queue is associated with a multi-function I/O device.

7. The apparatus of claim 1 , wherein the DVC comprises a virtualization layer and a physical layer, the virtualization layer exposes at least one peripheral device to the host computing device, and the physical layer provides an interface between a physical I/O device and the host computing device.

8. The apparatus of claim 7 , wherein the at least one peripheral device is a peripheral component interconnect express (PCIe) device.

9. The apparatus of claim 1 , wherein the DVC configures a virtual I/O device based at least in part on the host computing device detecting a peripheral device.

10. The apparatus of claim 1 , wherein the DVC is configured to map a function associated with a physical I/O device to a virtualized I/O device on the DVC to provide communication between the virtualized I/O device and the DVC.

11. A system, comprising:

a first host computing device including a first distributed virtualization controller (DVC) comprising circuitry physically disposed on the first host computing device;

a second host computing device including a second DVC comprising circuitry physically disposed on the second host computing device, wherein the first DVC and the second DVC are in communication with at least one virtualized input/output (I/O) device, wherein the first DVC is configured to virtualize the at least one virtualized I/O device to the first host computing device, and wherein the second DVC is configured to virtualize the at least one virtualize I/O device to the second host computing device; and

a network switch in communication with the first host computing device and the second host computing device.

12. The system of claim 11 , further comprising a management host computing device including a respective management host DVC, the management host computing device in communication with the switch.

13. The system of claim 11 , further comprising a plurality of queue base address registers (QBARs) associated with the at least one virtualized I/O device.

14. The system of claim 13 , wherein a first QBAR associated with the at least one virtualized I/O device is mapped to the first host computing device, and a second QBAR associated with the at least one virtualized I/O device is mapped to the second host computing device.

15. The system of claim 11 , wherein an I/O transaction from the I/O device traverses the network switch only once.

16. A distributed virtualization controller (DVC), comprising:

a virtualization layer input/output (I/O) processing block;

a physical layer I/O processing block; and

a queuing interface,

wherein the virtualization layer I/O processing block is configured to:

determine if an I/O transaction is to be forwarded to a physical I/O in communication with the DVC; and

forward the I/O transaction to a physical layer I/O processing block in response to the determination that the I/O transaction is to be forwarded, wherein the DVC is implemented in hardware physically coupled to a host computing device and wherein the DVC is configured to virtualize the I/O to the host computing device to which the DVC is physically coupled.

17. The DVC of claim 16 , wherein the host computing device is part of a distributed computing architecture.

18. The DVC of claim 16 , wherein the virtual layer I/O processing block is further configured to send a notification to a host computing device associated with the DVC in response to the I/O transaction being forwarded to the physical I/O.

19. The DVC of claim 16 , wherein the physical layer I/O processing block is further configured to receive a notification from the physical I/O in response to the I/O transaction being processed.

20. The DVC of claim 16 , wherein the physical layer I/O processing block is configured to:

modify an address associated with the I/O transaction; and

forward the I/O transaction to the physical I/O.

21. The DVC of claim 20 , wherein the physical layer I/O processing block is configured to modify an address associated with the I/O transaction concurrently with forwarding the I/O transaction to the physical I/O.

22. The DVC of claim 16 , wherein the I/O transaction is a storage command for a host bus adapter.

23. The DVC of claim 16 , wherein the I/O transaction is a descriptor for a network interface card.

24. A method, comprising:

receiving an input/output (I/O) transaction at a distributed virtualization controller (DVC) comprising circuitry physically coupled to a host computing device, wherein the DVC is configured to virtualize the I/O transaction to the host computing device on which the DVC is physically coupled;

identifying, in a virtualization layer associated with the DVC, a physical I/O to receive the I/O transaction; and

forwarding the I/O transaction to a physical layer associated with the DVC.

25. The method of claim 24 , further comprising modifying an address associated with the I/O transaction.

26. The method of claim 25 , further comprising modifying an address associated with the I/O transaction concurrently with receiving the I/O transaction at the DVC.

27. The method of claim 24 , further comprising generating, by the DVC, an error indication in response to an error being detected by the DVC.

28. The method of claim 27 , comprising generating the error indication in the form of an interrupt.

29. The method of claim 27 , further comprising initiating a recovery mechanism on the physical I/O in response to the error indication being generated.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037709 FRAME 0979. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 18, 2016
From: TCHAPDA, YVES
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037846/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: TCHAPDA, YVES
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037709/0979 →