Non-volatile semiconductor memory device
View Patent ↗Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.
1. A non-volatile semiconductor memory device comprising:
a substrate;
a stack structure, a plurality of the stack structures being arranged in a first direction along a surface of the substrate, the stack structure having a longitudinal direction, the longitudinal direction being a second direction along the surface of the substrate and crossing the first direction, the stack structure including a plurality of semiconductor layers, the semiconductor layers being stacked in a third direction crossing the first and second directions, the semiconductor layers having a longitudinal direction in the second direction, a lower semiconductor layer among the semiconductor layers having a larger length in the first direction than an upper semiconductor layer among the semiconductor layers;
a memory layer disposed on side surfaces in the first direction of the semiconductor layers; and
a conductive layer disposed on side surfaces in the first direction of the semiconductor layers via the memory layer, the conductive layer including a lower and an upper portion corresponding to the lower and the upper semiconductor layers, respectively, the lower portion having a larger length in the second direction than the upper portion,
wherein a predetermined portion in the upper semiconductor layer has a different impurity concentration from a predetermined portion in the lower semiconductor layer.
2. The device according to claim 1 , wherein
the upper semiconductor layer among the semiconductor layers has a larger length in the third direction than the lower semiconductor layer.
3. The device according to claim 1 , wherein
the predetermined portions correspond to channels of memory cells, and portions corresponding to sources/drains of the memory cell of the lower semiconductor layer have a higher impurity concentration than portions corresponding to sources/drains of the memory cell of the upper semiconductor layer.
4. The device according to claim 3 , wherein
the lower semiconductor layer among the semiconductor layers has a larger length in the third direction than the upper semiconductor layer.
5. The device according to claim 1 , wherein
the predetermined portions correspond to channels of memory cells, and the predetermined portion in the upper semiconductor layer has a higher impurity concentration than the predetermined portion in the lower semiconductor layer.
6. The device according to claim 5 , wherein
the upper semiconductor layer among the semiconductor layers has a larger length in the third direction than the lower semiconductor layer.
7. The device according to claim 1 , wherein
the lower semiconductor layer among the semiconductor layers has a larger length in the third direction than the upper semiconductor layer.
8. The device according to claim 1 , wherein
the conductive layer has a comb-blade shape, and comb-blade portions thereof each extends in the third direction.
9. The device according to claim 1 , wherein
each of the semiconductor layers includes a memory string having a plurality of memory cells connected in series.
10. A non-volatile semiconductor memory device comprising:
a substrate;
a stack structure, a plurality of the stack structures being arranged in a first direction along a surface of the substrate, the stack structure having a longitudinal direction, the longitudinal direction being a second direction along the surface of the substrate and crossing the first direction, the stack structure including a plurality of semiconductor layers, the semiconductor layers being stacked in a third direction crossing the first and second directions, and the semiconductor layers having a longitudinal direction in the second direction, a lower semiconductor layer among the semiconductor layers having larger length in the first direction than an upper semiconductor layer among the semiconductor layers, and the length of the upper semiconductor layer in the third direction being larger than the length of the lower semiconductor layer in the third direction; and
a memory layer disposed on side surfaces on the first direction of the semiconductor layers,
wherein a predetermined portion in the upper semiconductor layer has a different impurity concentration from a predetermined portion in the lower semiconductor layer.
11. The device according to claim 10 , further comprising
a conductive layer disposed on side surfaces on the first direction of the semiconductor layers via the memory layer,
the conductive layer including a lower and an upper portion corresponding to the lower and the upper semiconductor layers, respectively, the upper portion having a larger length in the second direction than the lower portion.
12. The device according to claim 11 , wherein
the conductive layer has a comb-blade shape, and comb-blade portions thereof each extend in the third direction.
13. The according to claim 10 , wherein
portions corresponding to sources/drains of memory cell of the lower semiconductor layer have a lower impurity concentration than portions corresponding to sources/drains of memory cell of the upper semiconductor layer.
14. The device according to claim 10 , wherein
each of the semiconductor layers includes a memory string having a plurality of memory cells connected in series.
15. A non-volatile semiconductor memory device comprising:
a substrate;
a stack structure, a plurality of the stack structures being arranged in a first direction along a surface of the substrate, the stack structure having a longitudinal direction, the longitudinal direction being a second direction along the surface of the substrate and crossing the first direction, the stack structure including a plurality of semiconductor layers, the semiconductor layers being stacked in a third direction crossing the first and second directions, and the semiconductor layers having a longitudinal direction in the second direction, a lower semiconductor layer among the semiconductor layers having larger length in the first direction than an upper semiconductor layer among the semiconductor layers;
a memory layer disposed on side surfaces in the first direction of the semiconductor layers; and
a conductive layer disposed on side surfaces on the first direction of the semiconductor layers via the memory layer, the conductive layer including a lower and an upper portion corresponding to the lower and the upper semiconductor layers, respectively, the upper portion having a larger length in the second direction than the lower portion,
wherein a predetermined portion in the upper semiconductor layer has a different impurity concentration from a predetermined portion in the lower semiconductor layer.
16. The device according to claim 15 , wherein
the predetermined portions correspond to channels of the memory cells, and the predetermined portion in the lower semiconductor layer has a higher impurity concentration than the predetermined portion in the upper semiconductor layer.
17. The device according to claim 15 , wherein
the predetermined portions correspond to channels of memory cells, and portions corresponding to sources/drains of the memory cell of the upper semiconductor layer have a higher impurity concentration than portions corresponding to sources/drains of the memory cell of the lower semiconductor layer.
18. The device according to claim 15 , wherein
the conductive layer has a comb-blade shape, and comb-blade portions thereof each extends in the third direction.
19. The device according to claim 15 , wherein each of the semiconductor layers includes a memory string having a plurality of memory cells connected in series.