Semiconductor device having a strained region
The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
1. A method of semiconductor fabrication, comprising:
providing a substrate having a fin;
forming a gate structure over the fin;
forming a recess in the fin adjacent the gate structure, wherein the recess includes a first sidewall, an opposing second sidewall and a bottom surface, wherein the first sidewall and opposing second sidewall extend from a top surface of the fin to an interface with the bottom surface of the recess;
after forming the recess, altering the first sidewall of the recess and the second sidewall of the recess by an ion implantation process thereby forming implanted regions extending along each of the first and second sidewalls, wherein a bottommost edge of the implanted regions is above the bottom surface of the recess; and
after the altering and without removing any portion of the first sidewall and the second sidewall, growing an epitaxial region in the recess, wherein the epitaxial region interfaces each of the implanted regions of the recess.
2. The method of claim 1 , wherein the ion implantation process includes a tilt implant.
3. The method of claim 2 , wherein the tilt implant is performed at an angle between approximately 10 degrees and approximately 60 degrees.
4. The method of claim 1 , wherein the ion implantation process includes implanting at least one of germanium, silicon, zenon, and carbon.
5. The method of claim 1 , further comprising:
implanting the grown epitaxial region with one of an n-type and a p-type dopant.
6. The method of claim 1 , wherein the epitaxial region in the recess is a strained epitaxial region.
7. The method of claim 1 , wherein the without removing any portion of the first sidewall and the second sidewall includes not performing an etching process on the first sidewall or the second sidewall after the altering and before the growing.
8. The method of claim 1 , further comprising:
forming another gate structure on the substrate; wherein the recess in the fin interposes the gate structure and the another gate structure.
9. The method of claim 8 , wherein the first sidewall of the recess is vertically aligned with a spacer element abutting the gate structure and the second sidewall of the recess is vertically aligned with a spacer element abutting the another gate structure.
10. A method of fabricating a semiconductor device, comprising:
providing a substrate having a fin;
forming a gate structure over the fin;
forming a recess in the fin adjacent the gate structure, wherein the recess is defined by a first sidewall and a second sidewall each having a length extending from a top surface of the substrate to a bottom wall of the recess;
implanting the first sidewall and the second sidewall of the recess, wherein an entirety of a length of the bottom wall of the recess is not implanted; and
after the implanting and without etching the length of the first and second sidewalls, growing an epitaxial region on the implanted first and second sidewalls such that the epitaxial region interfaces an entirety of the length of the first and second sidewalls and the bottom wall.
11. The method of claim 10 , wherein implant includes implanting at least one of germanium (Ge), silicon (Si), zenon (Xe), and carbon (C).
12. The method of claim 10 , wherein the implanting includes using a tilt angle of at least 10 degrees.
13. The method of claim 10 , wherein the implanting provides for a plurality of dislocations in a treatment region on the first and second sidewalls of the recess.
14. The method of claim 10 , wherein the forming the gate structure includes performing a replacement gate process to form a metal gate structure.
15. A method of forming a transistor, comprising:
etching a recess in a substrate, the recess having a first sidewall, an opposing second sidewall, and a bottom surface extending between the first and second sidewalls, wherein the etching forms the bottom surface including a first portion adjacent the first sidewall, a second portion adjacent the second sidewall, and a third portion interposing the first and second portions, wherein the first portion and the second portion are lower than the third portion;
growing an epitaxial layer in the recess including on the first and second sidewalls and the first, second, and third portions of the bottom surface;
using the grown epitaxial layer to provide a symmetrical stress on a channel region of the substrate; and
performing a junction implant on the grown epitaxial layer.
16. The method of claim 15 , further comprising providing the substrate including providing a fin element and wherein the etching the recess includes etching the recess in the fin element.
17. The method of claim 15 , wherein the etching the recess forms the recess having the bottom surface disposed at an angle of less than approximately 90 degrees with respect to a top surface of the substrate, wherein the bottom surface disposed at the angle is between the first portion and the third portion of the bottom surface.
18. The method of claim 17 , wherein the etching the recess also forms the recess having another portion of the bottom surface disposed at the angle of less than approximately 90 degrees with respect to the top surface of the substrate, wherein the another portion of bottom surface disposed at the angle is between the second portion and the third portion of the bottom surface.
19. The method of claim 15 , wherein the etching is at least one of dry etching and plasma etching.