IP Library Granted Patent US 9,892,767
Granted Patent B2
US 9,892,767 · App. 15/043,236 · Granted Feb 13, 2018

Data gathering in memory

Inventors: Jason T. Zawodny (Eagle, ID); Sanjay Tiwari (Meridian, ID); Richard C. Murphy (Boise, ID)
Assignee: Micron Technology, Inc.
G11C7/1012G11C5/06
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Quick Facts
Patent No.
US 9,892,767
App. No.
15/043,236
Granted
Feb 13, 2018
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Claims (52)

1. A method for gathering data, comprising:

storing a first element in memory cells coupled to a first sense line and a plurality of access lines;

storing a second element in memory cells coupled to a second sense line and the plurality of access lines, wherein the memory cells coupled to the first sense line are separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines; and

transferring the second element from being stored in the memory cells coupled to the second sense line to being stored in the memory cells coupled to the third sense line.

2. The method of claim 1 , wherein transferring the second element comprises reorganizing a data unit in a first position of the second element stored in a memory cell coupled to a first of the plurality of access lines and the second sense line to be stored in a memory cell coupled to the first of the plurality of access lines and the third sense line.

3. The method of claim 2 , wherein transferring the second element comprises reorganizing a data unit of the second element from being stored in a non-adjacent memory cell to being stored in an adjacent memory cell in relation to a memory cell storing a data unit of the first element.

4. The method of claim 3 , wherein the non-adjacent memory cell, the adjacent memory cell, and a memory cell storing a data unit in a first position of the first element are coupled to a same access line.

5. The method of claim 4 , wherein:

the first sense line is adjacent to the third sense line; and

at least one sense line is between the second sense line and the third sense line.

6. The method of claim 1 , comprising:

storing a third element in memory cells coupled to a fourth sense line and the plurality of access lines; and

storing the third element in memory cells coupled to a fifth sense line and the plurality of access lines, wherein the fifth sense line is between the third sense line and the second sense line.

7. The method of claim 6 , comprising performing a number of iterations of operations including at least one of an AND, an OR, and a SHIFT operation, wherein each iteration corresponds to storing a particular element.

8. The method of claim 7 , wherein a first of the number of iterations comprises storing the second element in the third sense line and a second of the number of iterations comprises storing the third element in the fifth sense line.

9. The method of claim 8 , wherein a third of the number of iterations comprises reorganizing a fourth element stored in memory cells coupled to a sixth sense line not between the fifth sense line and the second sense line to be stored in memory cells coupled to a seventh sense line that is between the fifth sense line and the second sense line.

10. The method of claim 9 , wherein the first sense line is adjacent to the third sense line, the third sense line is adjacent to the fifth sense line, and the fifth sense line is adjacent to the seventh sense line.

11. The method of claim 1 , wherein transferring the second element comprises performing at least one of a number of AND, OR, and SHIFT operations without transferring data via an input/output (I/O) line.

12. A method for gathering data, comprising:

storing a plurality of elements of a memory array, wherein:

each of the plurality of elements is stored in a respective group of memory cells coupled to a respective sense line and a plurality of access lines; and

each respective group of memory cells storing an element of the plurality of elements is separated from another group of memory cells storing an additional element of the plurality of elements by additional groups of memory cells, wherein each respective additional group of memory cells is coupled to a sense line and to the plurality of access lines; and

gathering the plurality of elements by reorganizing the plurality of elements such that a respective element is stored in a respective one of the additional groups of memory cells such that no memory cells are located between the memory cells storing the plurality of elements.

13. The method of claim 12 , wherein gathering the plurality of elements comprises reorganizing a first data unit of a first element to be stored in a memory cell adjacent to a memory cell storing a first data unit of a second element.

14. The method of claim 13 , wherein the first data unit of the first element is shifted a number of memory cells equal to a distance of memory cells from the first element to the second element minus one and multiplied by an iteration element number, wherein the iteration element number is one.

15. The method of claim 13 , wherein gathering the plurality of elements comprises shifting a first data unit of a third element to be stored in a memory cell adjacent to the memory cell storing the first data unit of the first element.

16. The method of claim 15 , wherein the first data unit of the third element is shifted a number of positions across memory cells equal to a distance of memory cells from the first element to the third element minus one multiplied by an additional iteration element number, wherein the additional iteration element number if two.

17. An apparatus, comprising:

a first group of memory cells coupled to a first sense line and to a plurality of access lines and configured to store a first element;

a second group of memory cells coupled to a second sense line and to the plurality of access lines, wherein the second sense line is adjacent to the first sense line;

a third group of memory cells coupled to a third sense line and to the plurality of access lines and configured to store a second element; and

a controller configured to operate sensing circuitry to perform a gather operation that includes reorganizing the second element from being stored in the third group of memory cells to being stored in the second group of memory cells.

18. The method of claim 17 , wherein the controller is configured to operate the sensing circuitry to perform the reorganizing without transferring data via an input/output (I/O) line.

19. The method of claim 17 , wherein the controller is configured to operate the sensing circuitry to perform the reorganizing without firing a column decode line.

20. The method of claim 17 , wherein the controller is configured to operate the sensing circuitry to reorganize the plurality of elements by performing a first iteration of operations that shifts the second element a number of columns of memory cells equal to a distance of the number of groups of memory cells between the first element and the second element.

21. The method of claim 20 , wherein the controller is configured to operate the sensing circuitry to shift the plurality of elements by performing a second iteration of operations that shifts a third element stored in a group of memory cells coupled to a fourth sense line a number of columns of memory cells equal to a distance from the group of memory cells coupled to the second sense line and the group of memory cells coupled to the fourth sense line.

22. An apparatus, comprising:

a plurality of first groups of memory cells, wherein each group of the plurality of first groups of memory cells is:

coupled to a respective sense line and to a plurality of access lines; and

configured to initially store an element of a plurality of elements;

a plurality of second groups of memory cells wherein:

each group of the plurality of second groups of memory cells is:

adjacent to at least one other group of the plurality of second groups of memory cells; and

between a first of the plurality of first groups of memory cells and a second of the plurality of first groups of memory cells; and

the plurality of second groups includes the first of the plurality of first groups of memory cells; and

a controller configured to operate sensing circuitry to gather elements initially stored in the plurality of first groups of memory cells to be stored in the plurality of second groups of memory cells.

23. The apparatus of claim 22 , wherein at least one sense line separates each of the respective sense lines from another of the respective sense lines that are coupled to the group of the plurality of first groups of memory cells.

24. The apparatus of claim 22 , wherein the group of memory cells store:

a first data unit of a first element in a memory cell coupled to a consecutively first sense line; and

a first data unit of a second element in a memory cell coupled to a consecutively N th sense line;

wherein memory cells coupled to the consecutively second, third, . . . , N th −1 access lines do not store an element and each of the plurality of elements are N−1 data units wide.

25. The apparatus of claim 22 , wherein each of the plurality of elements are stored in a group of memory cells coupled to the plurality of access lines and each of the respective sense lines.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2016
From: ZAWODNY, JASON T.; TIWARI, SANJAY; MURPHY, RICHARD C.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037729/0762 →
Continuity (1)
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