Granted Patent B2

US 10,164,004 · App. 15/045,490 · Granted Dec 25, 2018

Abstract

Claims (33)

1. A semiconductor device comprising:

a first insulating layer;

a first conductive layer partially embedded in the first insulating layer so that a part of the first conductive layer is exposed from the first insulating layer;

a second insulating layer covering an entirety of the exposed part of the first conductive layer such that an upper surface of the first conductive layer is in direct physical contact with and is covered by the second insulating layer, the second insulating layer being elongated over the first insulating layer to form a stacked insulating structure comprising the first and second insulating layers; and

a second conductive layer partially embedded in the stacked insulating structure so that a part of the second conductive layer is exposed from the stacked insulating structure, the second conductive layer not elevationally overlapping the first conductive layer.

2. The device of claim 1 , wherein the second conductive layer is in a cup shape to have a bottom portion, the bottom portion being embedded in the stacked insulating structure and the part of the second conductive layer extending upwardly from the bottom portion.

3. The device of claim 2 , further comprising:

a third conductive layer surrounding the second conductive layer; and

a dielectric film intervening between the second and the third conductive layers,

wherein the second and third conductive layers and the dielectric film cooperate with each other to serve as a capacitor.

4. A semiconductor device comprising:

a first insulating layer;

a first conductive layer partially embedded in the first insulating layer so that a part of the first conductive layer is exposed from the first insulating layer;

a second insulating layer covering the part of the first conductive layer, the second insulating layer being elongated over the first insulating layer to form a stacked insulating structure comprising the first and second insulating layers;

a second conductive layer partially embedded in the stacked insulating structure so that a part of the second conductive layer is exposed from the stacked insulating structure;

a third conductive layer surrounding the second conductive layer;

a dielectric film intervening between the second and the third conductive layers, the second and third conductive layers and the dielectric film cooperate with each other to serve as a capacitor; and

the third conductive layer is elongated over the stacked insulating structure, has laterally-outermost edges that extend laterally outward beyond laterally-outermost edges of the second conductive layer, and one of the laterally-outermost edges of the third conductive layer being laterally between the first and the second conductive layers.

5. The device of claim 3 , further comprising:

a third insulating layer covering continuously the third conductive layer and the second insulating layer,

wherein the second insulating layer intervenes between the third insulating layer and the part of the first conductive layer.

6. The device of claim 1 , wherein the first conductive layer penetrates the first insulating layer to form a first penetration part and the second conductive layer penetrates the stacked insulating structure to form a second penetration part, and wherein the device further comprises first and second contact plugs in electrical contact respectively with the first and second penetration parts.

7. A semiconductor device comprising:

a first insulating layer;

a first conductive layer partially embedded in the first insulating layer so that a part of the first conductive layer is exposed from the first insulating layer;

a second insulating layer covering an entirety of the exposed part of the first conductive layer with an upper surface of the first conductive layer being in direct physical contact with and covered by the second insulating layer, the second insulating layer being elongated over the first insulating layer to form a stacked insulating structure comprising the first and second insulating layers;

a second conductive layer partially embedded in the stacked insulating structure so that a part of the second conductive layer is exposed from the stacked insulating structure;

the first conductive layer penetrating the first insulating layer to form a first penetration part and the second conductive layer penetrating the stacked insulating structure to form a second penetration part;

first and second contact plugs in electrical contact respectively with the first and second penetration parts

first and second source/drain diffusion regions of different transistors, the first contact plug electrically connecting the first conductive layer to the first source/drain diffusion region and the second contact plug electrically connecting the second conductive layer to the second source/drain diffusion region.

8. The device of claim 7 , wherein the first source/drain diffusion region serves as a part of a peripheral transistor and the second source/drain diffusion region serves as a part of a memory cell transistor.

9. The device of claim 8 , wherein the second conductive layer serves as a lower electrode of a memory cell capacitor.

10. The device of claim 9 , further comprising a third insulating layer over the second insulating layer to cover the peripheral transistor, the third insulating layer being elongated to cover the memory cell capacitor.

Assignments (7)