Apparatuses and methods for multiple address registers for a solid state device
View Patent ↗The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus includes a controller including a plurality of base address registers (BARs) each including same addresses for data storage in a same memory resource and an SSD that includes the same memory resource.
1. An apparatus, comprising:
a controller comprising a plurality of base address registers (BARs) each including same addresses for data storage in a same memory resource; and
a solid state device (SSD) comprising the same memory resource; and wherein:
to enable performance of a write operation, the write operation is assigned to a first BAR that has a selected first cache attribute;
during performance of the write operation, data values of the write operation are assigned for storage to a particular buffer local to a processor before transfer to the SSD, wherein the particular buffer is controlled by the selected first cache attribute;
to enable performance of a read operation, the read operation is assigned to a second BAR that has a selected second cache attribute; and
during performance of the read operation, data values of the read operation are assigned for storage to a particular cache local to the processor after transfer from the SSD, wherein the particular cache is controlled by the selected second cache attribute.
2. The apparatus of claim 1 , wherein the controller is configured to assign an operation to one of the plurality of BARs as determined by which one of a plurality of types of operations is requested.
3. The apparatus of claim 1 , wherein:
the plurality of BARs each comprises a different cache attribute; and
the different cache attribute of each BAR corresponds to a type of operation that is requested.
4. The apparatus of claim 1 , wherein the SSD comprises NAND flash memory as a non-volatile memory resource.
5. The apparatus of claim 4 , wherein the SSD further comprises dynamic random access memory (DRAM) as a volatile memory resource.
6. The apparatus of claim 1 , wherein the SSD comprises 3D Point memory as a non-volatile memory resource.
7. The apparatus of claim 1 , wherein:
the plurality of BARs is more than two BARs selectably coupled to a plurality of partitions in a partitioned same memory resource; and
two BARs are selectably coupled to a first partition.
8. The apparatus of claim 1 , wherein the controller comprising the plurality of BARs is disposed on the SSD.
9. An apparatus, comprising:
a solid state device (SSD) driver; and
a controller comprising a plurality of base address registers (BARs) each configured to include same addresses for data storage in a same memory resource, wherein the controller is selectably coupled to the SSD driver; and
wherein the SSD driver, in combination with the controller, is configured to direct that:
a write operation type is assigned to a selected first BAR that has a selected first cache attribute that is enabled by the assignment to enable performance of a write operation;
during performance of the write operation, data values of the write operation are assigned for storage to a particular buffer local to a processor before transfer to the SSD, wherein the particular buffer is controlled by the selected first cache attribute;
a read operation type is assigned to a second BAR that has a selected second cache attribute that is enabled by the assignment to enable performance of a read operation; and
during performance of the read operation, data values of the read operation are assigned for storage to a particular cache local to the processor after transfer from the SSD, wherein the particular cache is controlled by the selected second cache attribute; and
wherein the first cache attribute is different from the second cache attribute.
10. The apparatus of claim 9 , wherein the SSD driver is further configured to:
receive a request for performance of an operation;
determine whether the requested operation is the read operation type or the write operation type; and
select a BAR from the plurality of BARs as appropriate for use with the determined operation type.
11. The apparatus of claim 9 , wherein:
an enabled cache attribute is assigned to a selected BAR; and
the enabled cache attribute is different from a cache attribute assigned to a non-selected BAR.
12. The apparatus of claim 9 , wherein an enabled first cache attribute is Write Combining.
13. The apparatus of claim 9 , wherein an enabled second cache attribute is Write Protected.
14. The apparatus of claim 9 , wherein the apparatus further comprises a host computing device comprising the processor and a primary memory resource.
15. The apparatus of claim 14 , wherein the plurality of BARs is two BARs selectably coupled to a same secondary memory resource.
16. The apparatus of claim 9 , wherein the apparatus further comprises an SSD comprising the same memory resource, wherein the plurality of BARs is selectably coupled to the same memory resource.
17. A method, comprising:
mapping of addresses for data storage in a secondary memory resource, the mapping set to Write Protected as a first cache attribute for a read operation request;
enabling performance of the requested read operation by assignment to a first base address register (BAR) that includes the mapped addresses set to the Write Protected first cache attribute;
during performance of the enabled read operation, assigning data values of the read operation for storage to a particular cache local to a host processor after transfer from a solid state device (SSD), wherein the particular cache is controlled by an enabled first cache attribute;
mapping of the addresses for data storage in a same secondary memory resource, the mapping set to Write Combining as a second cache attribute for a write operation request;
enabling performance of the requested write operation by assignment to a second BAR that includes the mapped addresses set to the Write Combining second cache attribute; and
during performance of the enabled write operation, assigning data values of the write operation for storage to a particular buffer local to the host processor before transfer to the SSD, wherein the particular buffer is controlled by an enabled second cache attribute; and
wherein the enabled first or second cache attribute is different from a cache attribute assigned to a non-selected BAR.
18. The method of claim 17 , wherein the method further comprises determining, by a SSD driver, whether a requested operation is the read operation request or the write operation request.
19. The method of claim 17 , wherein the method further comprises:
assigning, by a SSD driver, the requested read operation to the first BAR that includes the mapped addresses set to the Write Protected first cache attribute; and
assigning, by the SSD driver, the requested write operation to the second BAR that includes the mapped addresses set to the Write Combining second cache attribute.
20. The method of claim 17 , wherein the method further comprises:
enabling, by a SSD driver, the Write Protected first cache attribute assigned for the requested read operation for use with the first BAR that includes the mapped addresses; and
enabling, by the SSD driver, the Write Combining second cache attribute assigned for the requested write operation for use with the second BAR that includes the mapped addresses; and
wherein the first cache attribute for use with the first BAR and the second cache attribute for use with the second BAR are different cache attribute types.
21. The method of claim 17 , wherein the method further comprises registering the same addresses for data storage in the same secondary memory resource in the first BAR and the second BAR in a controller of the SSD when the SSD is initialized.
22. A system, comprising:
a host computing device comprising a central processing unit (CPU) and a primary memory resource;
a solid state device (SSD) driver selectably coupled to the CPU;
a controller, disposed on the SSD, configured to include a plurality of base address registers (BARs) each including same addresses for data storage in a same secondary memory resource, wherein the controller is selectably coupled to the SSD driver; and
the SSD comprising the same secondary memory resource, wherein the plurality of BARs is selectably coupled to the same secondary memory resource; and
wherein the SSD driver, in combination with the controller, is configured to direct that:
to enable performance of a read operation, the read operation is assigned to a first BAR that has a selected first cache attribute;
during performance of the read operation, a particular cache in the host computing device is assigned for storage of data values transferred from the same secondary memory resource for use by the CPU, wherein the particular cache is controlled by the selected first cache attribute;
to enable performance of a write operation, the write operation is assigned to a second BAR that has a selected second cache attribute;
during performance of the write operation, a particular buffer in the host computing device is assigned for use by the CPU for storage of data values to be transferred to the same secondary memory resource, wherein the particular buffer is controlled by the selected second cache attribute; and
wherein the selected first cache attribute of the first BAR and the selected second cache attribute of the second BAR are different cache attribute types.
23. The system of claim 22 , wherein a volatile memory resource is the primary memory resource.
24. The system of claim 22 , wherein non-volatile 3D XPoint memory is the same secondary memory resource.
25. The system of claim 22 , wherein the apparatus further comprises a peripheral component interconnect express (PCIe) bus as a communication interface between the host computing device, the SSD driver, a peripheral SSD comprising the same secondary memory resource, and the controller to form a PCIe circuit.
26. The system of claim 22 , wherein the SSD driver is disposed on the host computing device.
27. The system of claim 22 , wherein:
the particular cache in the host computing device is assigned by the device SSD driver for storage of data values transferred from the same secondary memory resource; and
the particular cache is controlled by an enabled first cache attribute.
28. The system of claim 27 , wherein the enabled first cache attribute is Write Protected for the read operation.
29. The system of claim 22 , wherein:
the particular cache in the host computing device is selected by the device SSD driver for use by the CPU in performance of the read operation; and
the particular cache is an internal cache that is part of the CPU.
30. The system of claim 22 , wherein:
the particular cache in the host computing device is selected by the SSD driver for use by the CPU in performance of the read operation; and
the particular cache is a cache that is external to the CPU.
31. The system of claim 22 , wherein:
The particular buffer in the host computing device is assigned by the device SSD driver for storage of data values to be transferred to the same secondary memory resource; and
the particular buffer is controlled by an enabled Write Combining as the second cache attribute.
32. The system of claim 22 , wherein the particular buffer in the host computing device is selected by the SSD driver for use by the CPU for transfer of the data.