Storage system and storage control circuit
View Patent ↗A storage system capable of retaining data even when power supply is stopped is provided. A storage system capable of reducing power that is necessary for retaining data is provided. A memory cell including a transistor with low off-state current is used as a cache memory. By utilizing the low off-state current, data is retained and refreshed at a frequency of approximately once an hour, whereby data can be retained semi-permanently. When power supply is temporarily stopped, data is retained using power which allows the transistor to be kept off, whereby power can be drastically reduced as compared with a configuration in which data is backed up.
1. A storage system comprising:
a storage;
a storage control circuit; and
a host,
wherein the storage control circuit comprises a controller, a cache memory, and a power storage device,
wherein the controller controls data input and output between the storage and the host by access of the host,
wherein the cache memory comprises a first transistor,
wherein the first transistor retains a charge based on the data by being turned off,
wherein the power storage device supplies power for turning off the first transistor in a state where power supply from outside is stopped, and
wherein, in the state where power supply from outside is stopped, the power storage device supplies power to the cache memory at regular intervals.
2. The storage system according to claim 1 , wherein the first transistor comprises an oxide semiconductor in a channel formation region.
3. The storage system according to claim 1 , further comprising a capacitor,
wherein the first transistor is electrically connected to the capacitor, and
wherein the first transistor retains the charge based on the data in the capacitor by being turned off.
4. The storage system according to claim 1 , further comprising a second transistor and a node,
wherein the node is electrically connected to one of a source electrode and a drain electrode of the first transistor and a gate electrode of the second transistor, and
wherein the first transistor retains the charge based on the data in the node by being turned off.
5. The storage system according to claim 1 , further comprising a timer,
wherein the storage control circuit comprises the timer,
wherein the data is refreshed before the timer starts to measure a period in the state where power supply from outside is stopped, and
wherein the data is refreshed under control of the timer after the timer starts to measure the period in the state where power supply from outside is stopped.
6. The storage system according to claim 1 , wherein the power storage device is a secondary battery.
7. The storage system according to claim 1 , wherein, in the state where power supplied from outside is stopped, the data in the cache memory is refreshed intermittently.
8. A storage control circuit comprising:
a controller;
a cache memory; and
a power storage device,
wherein the controller controls data input and output between a storage and a host by access of the host,
wherein the cache memory comprises a first transistor,
wherein the first transistor retains a charge based on the data by being turned off,
wherein the power storage device supplies power for turning off the first transistor in a state where power supply from outside is stopped, and
wherein, in the state where power supply from outside is stopped, the power storage device supplies power to the cache memory at regular intervals.
9. The storage control circuit according to claim 8 , wherein the first transistor comprises an oxide semiconductor in a channel formation region.
10. The storage control circuit according to claim 8 , further comprising a capacitor,
wherein the first transistor is electrically connected to the capacitor, and
wherein the first transistor retains the charge based on the data in the capacitor by being turned off.
11. The storage control circuit according to claim 8 , further comprising a second transistor and a node,
wherein the node is electrically connected to one of a source electrode and a drain electrode of the first transistor and a gate electrode of the second transistor, and
wherein the first transistor retains the charge based on the data in the node by being turned off.
12. The storage control circuit according to claim 8 , wherein the power storage device is a secondary battery.
13. The storage control circuit according to claim 8 , further comprising a timer,
wherein the data is refreshed before the timer starts to measure a period in the state where power supply from outside is stopped, and
wherein the data is refreshed under control of the timer after the timer starts to measure the period in the state where power supply from outside is stopped.
14. The storage control circuit according to claim 8 , wherein, in the state where power supplied from outside is stopped, the data in the cache memory is refreshed intermittently.