Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a substrate including cell and dummy regions, first channel structures on the cell region and extending in a first direction vertical with respect to the substrate, gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the substrate, the gate lines being spaced apart from each other along the first direction, cutting lines between the gate lines on the cell region and extending in the second direction, dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that in the gate lines, and dummy lines through the dummy patterns.
1. A semiconductor device, comprising:
a substrate including a cell region and a dummy region;
first channel structures on the cell region of the substrate, the first channel structures extending in a first direction vertical with respect to a top surface of the substrate;
gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the top surface of the substrate, the gate lines being spaced apart from each other along the first direction;
cutting lines between the gate lines on the cell region, the cutting lines extending in the second direction;
dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that included in the gate lines; and
dummy lines extending through the dummy patterns, the dummy lines having a different configuration than the cutting lines in a top view.
2. The semiconductor device as claimed in claim 1 , wherein the dummy region is adjacent to an end portion of the cell region in the third direction.
3. The semiconductor device as claimed in claim 1 , wherein the dummy lines include a same conductive material as that included in the cutting lines.
4. The semiconductor device as claimed in claim 1 , wherein the dummy lines extend in the third direction and perpendicularly to the cutting lines.
5. The semiconductor device as claimed in claim 4 , wherein a distance between the dummy lines is equal to or greater than a distance between the cutting lines.
6. The semiconductor device as claimed in claim 4 , wherein:
at least one of the dummy patterns includes conductive patterns spaced apart in the second direction, and a sacrificial pattern interposed between the conductive patterns, and
the conductive patterns include a same conductive material as that of the gate lines, and the sacrificial pattern includes a nitride.
7. The semiconductor device as claimed in claim 1 , wherein the dummy lines extend in a fourth direction diagonal to the second direction.
8. The semiconductor device as claimed in claim 1 , wherein the dummy lines extend in the second direction.
9. The semiconductor device as claimed in claim 8 , wherein a first portion of the dummy patterns includes a same conductive material as that of the gate lines, and a second portion of the dummy patterns different than the first portion includes a conductive pattern and a sacrificial pattern, the conductive pattern including the conductive material and the sacrificial pattern including a nitride.
10. The semiconductor device as claimed in claim 1 , wherein the dummy patterns are positioned at corresponding levels of the gate lines.
11. The semiconductor device as claimed in claim 1 , further comprising insulating interlayer patterns between the dummy patterns neighboring in the first direction and between the gate lines neighboring in the first direction.
12. The semiconductor device as claimed in claim 1 , wherein the cutting lines are common source lines, and the dummy lines are dummy source lines having a different shape or direction from the common source lines, as viewed in the top view.
13. The semiconductor device as claimed in claim 1 , further comprising a third channel structure extending through the dummy patterns on the dummy region of the substrate.
14. The semiconductor device as claimed in claim 1 , further comprising a dummy cell on a portion of the cell region adjacent to the dummy region.
15. A semiconductor device, comprising:
a substrate including a cell region and a dummy region;
first channel structures on the cell region of the substrate, the first channel structures extending in a first direction vertical with respect to a top surface of the substrate;
gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the top surface of the substrate, the gate lines being spaced apart from each other along the first direction;
first insulating interlayer patterns between gate lines neighboring to each other in the first direction;
cutting lines interposed between the gate lines on the cell region, the cutting lines extending in the second direction;
dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that included in the gate lines;
second insulating interlayer patterns between dummy patterns neighboring each other in the first direction; and
dummy lines extending through the dummy patterns and the second insulating interlayer patterns, the dummy lines having a different configuration than the cutting lines in a top view.
16. A semiconductor device, comprising:
a substrate including a cell region and a dummy region;
first channel structures on the cell region of the substrate, the first channel structures extending in a first direction vertical with respect to a top surface of the substrate;
gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the top surface of the substrate, the gate lines being spaced apart from each other along the first direction;
common source lines between the gate lines on the cell region, the common source lines extending in the second direction;
dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that included in the gate lines; and
dummy source lines extending through the dummy patterns, the dummy source lines having a different direction or shape than the common source lines in a top view.
17. The semiconductor device as claimed in claim 16 , wherein the dummy source lines extend from an outermost side of the dummy region toward the cell region in a different direction than the common source lines, as viewed in the top view.
18. The semiconductor device as claimed in claim 17 , wherein a distance between neighboring dummy source lines is greater than a distance between neighboring common source lines.
19. The semiconductor device as claimed in claim 17 , wherein the dummy source lines and the common source lines include a same conductive material.
20. The semiconductor device as claimed in claim 16 , wherein the dummy source lines are a plurality of dummy source line segments spaced apart from each other in at least one of the second and third directions.