Modified decode for corner turn
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
1. An apparatus comprising:
an array of memory cells; and
decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element;
wherein the logic is configured to modify the address corresponding to the at least one data element on a per column select basis; and
wherein the corner turn operation is an operation that adjusts a storage format of the at least one data element.
2. The apparatus of claim 1 , wherein the decode circuitry comprises a plurality of column select components each coupled to a respective N columns of the array, wherein “N” is at least 2.
3. The apparatus of claim 2 , wherein the at least one data element comprises an M-bit wide data element, and wherein M is equal to N.
4. The apparatus of claim 2 , wherein the address corresponding to the at least one data element comprises a plurality of address data units, and wherein the logic configured to modify the address corresponding to the at least one data element comprises:
first logic configured to modify a first address data unit of the plurality of address data units prior to the plurality of address data units being provided to a first of the plurality of column select components; and
second logic configured to modify a second address data unit of the plurality of address data units prior to the plurality of address data units being provided to a second of the plurality of column select components.
5. The apparatus of claim 4 , wherein the logic configured to modify the address corresponding to the at least one data element further comprises:
third logic configured to modify the first address data unit and the second address data unit of the plurality of address data units prior to the plurality of address data units being provided to a third of the plurality of column select components; and
fourth logic configured to modify a third address data unit of the plurality of address data units prior to the plurality of address data units being provided to a fourth of the plurality of column select components; and
fifth logic configured to modify the first, second, and third address data units prior to the plurality of address data units being provided to a fifth of the plurality of column select components.
6. The apparatus of claim 4 , wherein:
the first logic comprises a logic gate configured to receive the first address data unit and an enable data unit as inputs and invert the first address data unit responsive to a state of the enable data unit; and
the second logic comprises a logic gate configured to receive the second address data unit and an enable data unit as inputs and invert the second address data unit responsive to a state of the enable data unit.
7. The apparatus of claim 4 , wherein at least one of the first logic gate and the second logic gate comprises an exclusive OR (XOR) logic gate.
8. The apparatus of claim 4 , wherein the plurality of column select components each comprise a respective N:1 multiplexor.
9. The apparatus of claim 1 , wherein the array and decode circuitry are located on a controller configured to:
receive the at least one data element from a host;
write the at least one data unit to the array based on the modified address corresponding thereto;
read the at least one data unit out of the array based on the modified address; and
write the at least one data element to a different array of memory cells such that the at least one data element is stored in a consecutive number of memory cells coupled to a same column of the different array.
10. An apparatus, comprising:
a corner turn buffer comprising an array of memory cells configured to store data elements, the corner turn buffer used to adjust a storage format of a data element from a first format to a second format; and
decode circuitry coupled to the array and comprising:
a plurality of N:1 column select components each corresponding to a different respective N columns of the array and configured to select a particular one of the N columns responsive to states of a plurality of address data units provided thereto and corresponding to the data element; and
address modification logic coupled to at least one of the plurality of column select components and configured to modify a state of at least one of the plurality of address data units corresponding to the data element and prior to the plurality of address data units being provided to the at least one of the plurality of column select components in association with at least one of:
writing the data element to the array; and
reading the data element from the array.
11. The apparatus of claim 10 , wherein the address modification logic comprises a logic gate configured to:
receive the at least one of the plurality of address data units as a first input;
receive at least one enable data unit as a second input;
invert the at least one of the plurality of address data units; and
provide the inverted data unit as an output.
12. The apparatus of claim 11 , wherein the logic gate comprises an exclusive OR (XOR) logic gate.
13. The apparatus of claim 10 , wherein the address modification logic is configured to modify the state of the at least one of the plurality of address data units differently for each of the at least one of the plurality of column select components.
14. The apparatus of claim 10 , wherein the data element comprises an M-bit wide data element, and the plurality of address data units comprises log 2 (M) bits, and wherein values of the plurality of address data units correspond to respective bit positions within the data element.
15. The apparatus of claim 14 , wherein M is 8 and N is 8.
16. The apparatus of claim 10 , further comprising a counter configured to provide the plurality of address data units at its output.
17. The apparatus of claim 10 , wherein the address modification logic is configured to modify the state of the at least one of the plurality of address data units corresponding to the data element in association with only one of:
writing the data element to the array; and
reading the data element from the array.
18. The apparatus of claim 10 , further comprising a controller, wherein the corner turn buffer and the decode circuitry are located on the controller, and wherein the controller is configured to:
read the data element from the array; and
write the data element to a different array to which the controller is coupled such that the data element is stored vertically in the different array.
19. The apparatus of claim 10 , further comprising a channel controller, wherein the corner turn buffer and the decode circuitry are located on the channel controller, and wherein the channel controller is configured to communicate with a memory controller configured to:
receive the data element from the corner turn buffer; and
write the data element to a different array to which the memory controller is coupled such that the data element is stored vertically in the different array.
20. An apparatus comprising:
a controller configured to write a data element received from a host to a first array of memory cells of a corner turn buffer in association with performing a corner turn operation on the data element, wherein the corner turn operation is an operation that adjusts a storage format of the data element;
wherein the corner turn buffer comprises decode circuitry coupled to the first array and comprising:
a plurality of column select components each coupled to a respective plurality of columns of the first array; and
address modification logic coupled to at least one of the plurality of column select components and configured to modify a state of at least one of a plurality of address data units corresponding to the data element and prior to the plurality of address data units being provided to the at least one of the plurality of column select components in association with writing the data element to the first array; and
wherein the controller is further configured to:
read the data element out of the first array; and
write the data element in cells coupled to a same column of and to a number of different access lines of a second array.
21. The apparatus of claim 20 , wherein the second array is coupled to sensing circuitry comprising a plurality of sense amplifiers and compute components.
22. The apparatus of claim 21 , wherein the plurality of sense amplifiers and compute components correspond to a respective plurality of columns of the second array and are configured to serve as a respective plurality of 1-bit processing resources.