Scheme to avoid miscorrection for turbo product codes

1. A method of operating a memory system including a controller and a memory device coupled with the controller, comprising:

receiving data, by the controller, from the memory device, wherein the controller includes an ECC unit;

detecting errors in the received data by the ECC unit;

identifying a stuck error pattern including failing constituent codes in the detected errors by the ECC unit; and

decoding the stuck error pattern by the ECC unit, including:

using possible flipping patterns for decoding the failing constituent codes, wherein the number of the possible flipping patterns is 2 n k in accordance with at least the number of error bits n of kth failing constituent code;

obtaining a number of successfully decoded codewords after using the possible flipping patterns, and

selecting the most probable codeword from the number of successfully decoded codewords.

2. The method of claim 1 , wherein the using possible flipping patterns includes using all possible flipping patterns for decoding each of the failing constituent codes.

3. The method of claim 1 , wherein the number of successfully decoded codewords obtained is equal to one.

4. The method of claim 1 , wherein the selecting step includes:

determining a codeword that satisfies a predetermined number of criteria as the most probable codeword.

5. The method of claim 4 , wherein the criteria include at least one of having all bit corrections made in error intersection regions, having a least number of corrected bits, and having a greatest number of successfully decoded column/rows.

6. The method of claim 4 , further comprising skipping decoding of the constituent codes when the predetermined number of criteria are not satisfied.

7. The method of claim 1 , further comprising constructing a list including the number of successfully decoded codewords.

8. A memory system, comprising:

a post-processor for correcting data;

a non-transitory computer readable storage medium coupled to the post-processor, embedding computer program product executed by the post-processor, and including computer instructions configured to:

control memory devices;

receive data, by the controller, from a memory device, wherein the controller includes an ECC unit;

detect errors in the received data by the ECC unit;

identify a stuck error pattern including failing constituent codes in the detected errors by the ECC unit;

use possible flipping patterns for decoding failing constituent codes of the stuck error pattern, wherein the number of the possible flipping patterns is 2 n k in accordance with at least the number of error bits n of kth failing constituent code;

obtain a number of successfully decoded codewords after using the possible flipping patterns; and

select the most probable codeword from the number of successfully decoded codewords; and

a stuck turbo product code decoder configured to receive the data corrected by the post-processor.

9. The memory system of claim 8 , wherein the post-processor is further configured to use all possible flipping patterns for decoding each of the failing constituent codes.

10. The memory system of claim 8 , wherein the number of successfully decoded codewords obtained is equal to one.

11. The memory system of claim 8 , wherein the post-processor is further configured to select the most probable codeword from the number of successfully decoded codewords by determining a codeword that satisfies a predetermined number of criteria as the most probable codeword.

12. The memory system of claim 11 , wherein the criteria include at least one of having all bit corrections made in error intersection regions, having a least number of corrected bits, and having a greatest number of successfully decoded column/rows.

13. The memory system of claim 11 , wherein the post-processor is further configured to skip decoding of the constituent codes when the predetermined number of criteria are not satisfied.

14. The memory system of claim 8 , wherein the controller is further configured to construct a list including the number of successfully decoded codewords.

15. An apparatus of a memory system, comprising:

memory devices; and

a controller coupled with the memory devices, configured to:

receive data, by the controller, from at least one of the memory devices, wherein the controller includes an ECC unit;

detect errors in the received data by the ECC unit;

identify a stuck error pattern including failing constituent codes in the detected errors by the ECC unit;

use possible flipping patterns for decoding failing constituent codes of the stuck error pattern, wherein the number of the possible flipping patterns is 2 n k in accordance with at least the number of error bits n of kth failing constituent code;

obtain a number of successfully decoded codewords after using the possible flipping patterns; and

select the most probable codeword from the number of successfully decoded codewords.

16. The apparatus of claim 15 , wherein the controller is configured to select the most probable codeword from the number of successfully decoded codewords by determining a codeword that satisfies a predetermined number of criteria as the most probable codeword.

17. The apparatus of claim 16 , wherein the criteria include at least one of having all bit corrections made in error intersection regions, having a least number of corrected bits, and having a greatest number of successfully decoded column/rows.

18. The apparatus of claim 16 , wherein the controller is configured to skip decoding of the constituent codes when the predetermined number of criteria are not satisfied.