IP Library Granted Patent US 10,193,334
Granted Patent B2
US 10,193,334 · App. 15/050,238 · Granted Jan 29, 2019

Apparatuses and method for over-voltage event protection

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Quick Facts
Patent No.
US 10,193,334
App. No.
15/050,238
Granted
Jan 29, 2019
Kind
B2
Abstract

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

Claims (27)

1. An apparatus, comprising:

a conductive path circuit configured to discharge current associated with an over-voltage event at an input node responsive to a voltage of the input node having a magnitude that exceeds a trigger voltage; and

a trigger circuit coupled to the conductive path circuit, the trigger circuit comprising:

a first transistor coupled to the conductive path circuit and configured to adjust the magnitude of the trigger voltage, wherein the trigger voltage is provided from a source of the first transistor, wherein the first transistor comprises a p-type field-effect transistor including a drain, wherein a doped region forming the drain of the first transistor is shared with the conductive path circuit; and

a lateral bipolar junction transistor merged with the first transistor and wherein the first transistor and the bipolar junction transistor share at least two doped regions.

2. The apparatus of claim 1 , wherein the conductive path circuit shares at least two doped regions with the trigger circuit.

3. The apparatus of claim 2 , wherein the conductive path circuit comprises a negative direction silicon controlled rectifier configured to limit voltage between a reference node and the input node responsive to a magnitude of voltage differential between the input node and the reference node being more negative than the trigger voltage.

4. The apparatus of claim 3 , wherein the negative direction silicon controlled rectifier shares a drain of the first transistor.

5. The apparatus of claim 4 , where in the silicon controlled rectifier comprises a first hi-polar junction transistor coupled to a second bi-polar junction transistor, wherein the first bi-polar junction transistor is coupled to the input node and the second hi-polar junction transistor is coupled to a reference node.

6. The apparatus of claim 1 , wherein the lateral bipolar junction transistor includes an emitter region that is shared with the drain of the p-type field-effect transistor.

7. The apparatus of claim 1 , wherein the first transistor comprises a p-type field-effect transistor including a gate configured to receive a voltage to which the first transistor is responsive to adjust the magnitude of the trigger voltage.

8. The apparatus of claim 1 , wherein the lateral bipolar junction transistor includes an emitter region that is shared with the conductive circuit.

9. An apparatus, comprising:

a protected circuit coupled to an input node;

a protection circuit coupled to the input node in parallel with the protected circuit, the protection circuit including a conductive path circuit and a trigger circuit, the conductive path circuit coupled to the input node and a reference node and configured to provide a negative discharge path between the input node and the reference node responsive to an over-voltage event at the input node, wherein the trigger circuit is coupled to the conductive path circuit and is configured to adjust the trigger voltage responsive to a voltage of a control node of the trigger circuit, wherein the trigger voltage is provided from a source of a trigger transistor of the trigger circuit to the conductive path circuit, wherein the trigger transistor comprises a p-type field-effect transistor including a drain, wherein a doped region forming the drain of the trigger transistor is shared with the conductive path circuit.

10. The apparatus of claim 9 , wherein the trigger circuit is coupled to a control node, wherein the trigger voltage is adjusted by the trigger circuit based on a voltage of the control node.

11. The apparatus of claim 9 , wherein the trigger circuit is configured to adjust the magnitude of the trigger voltage to a first voltage while in a first state and to a second voltage while in a second state.

12. The apparatus of claim 11 , wherein the first voltage is more negative than the second voltage.

13. The apparatus of claim 9 , wherein the trigger circuit includes a trigger bipolar junction transistor, and a body of the trigger transistor shares an n-well with at least a portion of the trigger bipolar junction transistor.

14. An apparatus, comprising:

a protected circuit coupled to an input node;

a protection circuit coupled to the input node in parallel with the protected circuit, the protection circuit including a conductive path circuit and a trigger circuit, the conductive path circuit configured to discharge a current associated with an over-voltage event at the input node responsive to a trigger voltage, wherein the trigger circuit is configured to adjust the magnitude of the trigger voltage, and the trigger circuit includes a trigger bipolar junction transistor merged with a trigger field-effect transistor, wherein the trigger voltage is provided from a source of the trigger field-effect transistor to the conductive path circuit, wherein the trigger field-effect transistor comprises a p-type field-effect transistor including a drain, wherein a doped region forming the drain of the p-type field-effect transistor is shared with the conductive path circuit.

15. The apparatus of claim 14 , wherein the conductive path circuit shares with the trigger circuit a first well doped with a first dopant type, and a second well doped with a second dopant type.

16. The apparatus of claim 15 , wherein the first dopant type is an n-type dopant and the second dopant type is a p-type dopant.

17. The apparatus of claim 14 , wherein the conductive path circuit comprises a silicon controlled rectifier.

18. The apparatus of claim 14 , wherein the trigger bipolar junction transistor comprises a PNP bipolar junction transistor.

19. The apparatus of claim 14 , wherein the conductive path circuit is configured to discharge the current associated with the over-voltage event at the input node responsive to a magnitude of a voltage difference between the input node and a reference node exceeding the trigger voltage.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →