Semiconductor storage device and processor system
View Patent ↗A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,
1. A semiconductor storage device comprising:
a non-volatile memory;
a memory controller to carry out write processing to the non-volatile memory using a write pulse; and
a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory.
2. The semiconductor storage device according to claim 1 , wherein
the write pulse includes a first write pulse and a second write pulse having a longer pulse width than the first write pulse, and
when the first write mode is selected, the write pulse controller selects the second write pulse as the write pulse when the pulse width of the second write pulse is shorter than one cycle of the clock signal, while selecting the first write pulse as the write pulse when the pulse width of the second write pulse is longer than one cycle of the clock signal.
3. The semiconductor storage device according to claim 2 , wherein
when the second write mode is selected, the write pulse controller selects the first write pulse as the write pulse.
4. The semiconductor storage device according to claim 1 , wherein
the write pulse controller selects the first write mode or the second write mode based on a state signal indicating an operating state of a processor.
5. The semiconductor storage device according to claim 4 , wherein
the write pulse controller comprises
a pulse selector to select, based on the state signal, one pulse signal from among a plurality of pulse signals having different pulse widths from each other; and
a voltage selector to select, based on the state signal, one voltage from among a plurality of voltages having different voltage levels from each other, and
the write pulse controller controls the write pulse based on the pulse signal selected by the pulse selector and the voltage selected by the voltage selector.
6. The semiconductor storage device according to claim 5 , wherein
the non-volatile memory comprises a plurality of memory elements,
the write pulse controller comprises a transistor serially connected to each of the plurality of memory elements and to be turned on or off based on the pulse signal selected by the pulse selector, and
the voltage selected by the voltage selector is applied to the memory element corresponding to the transistor while the transistor is being turned on.
7. The semiconductor storage device according to claim 5 , wherein
the write pulse controller comprises:
a memory operation monitor to observe an operating state of the non-volatile memory,
the pulse selector selects one pulse signal from among the plurality of pulse signals based on the state signal and observation results by the memory operation monitor, and
the voltage selector selects one voltage from among the plurality of voltages based on the state signal and observation results by the memory operation monitor.
8. The semiconductor storage device according to claim 7 , wherein
the memory operation monitor comprises:
an access history storage to store at least one of access interval(s) of the n time(s) (where n is an integer equal to or larger than one) and an access distribution for the m time(s) (where m is an integer equal to or larger than one) to the non-volatile memory; and
a pulse determinator to determine the pulse signal to be selected by the pulse selector, based on the state signal and the observation results including at least one of the access interval(s) of n time(s) and the access distribution for m time(s).
9. The semiconductor storage device according to claim 1 , further comprising a plurality of memory blocks capable of being accessed per block and each including the non-volatile memory, wherein
the write pulse controller controls the write pulse for each of the plurality of memory blocks based on an operating state of a corresponding memory block and an operating state of a processor.
10. The semiconductor storage device according to claim 1 , further comprising a cache memory, wherein
the cache memory comprises:
a cache data storage including the non-volatile memory, the cache data storage storing cache data; and
a tag storage including the non-volatile memory, the tag storage storing address information on the cache data, and
the write pulse controller writes data to the cache data storage and the tag storage using the write pulse.
11. The semiconductor storage device according to claim 1 further comprising a cache memory, wherein
the cache memory comprises:
a cache data storage including the non-volatile memory, the cache data storage storing cache data; and
a tag storage including a volatile memory, the tag storage storing address information on the cache data, and
the write pulse controller writes data to the cache data storage using the write pulse.
12. The semiconductor storage device according to claim 10 , further comprising a write buffer to which data to be stored to the cache memory is stored, wherein
the write pulse controller controls the write pulse based on an occupation rate of the write buffer and a state signal indicating a state of a processor.
13. The semiconductor storage device according to claim 12 , wherein
the cache memory comprises a plurality of memory blocks, and
the write pulse controller controls the write pulse to the plurality of memory blocks based on the state signal and an operating state of the plurality of memory blocks.
14. The semiconductor storage device according to claim 1 , wherein
the non-volatile memory is a magnetoresistive random access memory (MRAM).
15. A processor system comprising:
a processor core;
a cache memory comprising a cache data storage and a tag storage, the cache data storage including a non-volatile memory;
a memory controller to carry out write processing to the non-volatile memory using a write pulse; and
a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory, wherein
a cache data storage stores cache data; and
a tag storage stores address information on the cache data, and
the write pulse controller writes data to the cache data storage using the write pulse.
16. The processor system according to claim 15 , wherein
the tag storage comprises the non-volatile memory; and
the write pulse controller writes data to the cache data storage and the tag storage using the write pulse.
17. The processor system according to claim 15 , wherein
the write pulse includes a first write pulse and a second write pulse having a longer pulse width than the first write pulse, and
when the first write mode is selected, the write pulse controller selects the second write pulse as the write pulse when the pulse width of the second write pulse is shorter than one cycle of the clock signal, while selecting the first write pulse as the write pulse when the pulse width of the second write pulse is longer than one cycle of the clock signal.
18. The processor system according to claim 17 , wherein
when the second write mode is selected, the write pulse controller selects the first write pulse as the write pulse.
19. The processor system according to claim 15 , wherein
the write pulse controller selects the first write mode or the second write mode based on a state signal indicating an operating state of a processor.
20. The processor system according to claim 19 , wherein
the write pulse controller comprises:
a pulse selector to select, based on the state signal, one pulse signal from among a plurality of pulse signals having different pulse widths from each other; and
a voltage selector to select, based on the state signal, one voltage from among a plurality of voltages having different voltage levels from each other, and
the write pulse controller controls the write pulse based on the pulse signal selected by the pulse selector and the voltage selected by the voltage selector.