Digital fractional-N PLL based upon ring oscillator delta-sigma frequency conversion
View Patent ↗A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.
1. A digital fractional-N phase locked loop, comprising:
a delta-sigma frequency-to-digital converter including an input to a phase-frequency detector, a dual-mode ring oscillator including a plurality of delay elements and being driven by an output of the phase-frequency detector, a ring phase calculator that samples outputs of the dual-mode ring oscillator to calculate phase of the dual-mode ring oscillator, and a local feedback path through a digital linear filter and a divider to the phase-frequency detector;
a digital loop filter to suppress quantization noise of the delta-sigma frequency-to-digital converter and noise from other circuit blocks; and
a digital controlled oscillator controlled by the output of the digital loop filter to provide the PLL output and feedback to the delta-sigma frequency-to-digital converter, wherein the divider has a modulus that is split into fixed and variable count intervals such that the modulus for the variable count interval need not be loaded until a predetermined number of digitally controlled oscillator periods before the end of a reference period.
2. The digital fractional-N phase locked loop of claim 1 , wherein the dual-mode ring oscillator switches between high and low frequency operation in response to high and low output levels of the phase-frequency detector.
3. The digital fractional-N phase locked loop of claim 1 , wherein the ring phase calculator samples outputs of the plurality of delay elements to generate a sequence −ê q [n] that is a measure of quantization error in the dual-mode ring oscillator and samples the output of an C-bit counter to generate a sequence y[n] that is a measure of the phase of the dual-mode ring oscillator.
4. The digital fractional-N phase locked loop of claim 3 , wherein the ring phase calculator measures quantization error to a resolution that is a fraction of a cycle of the dual-mode ring oscillator.
5. The digital fractional-N phase locked loop of claim 3 , wherein the ring phase calculator further comprises a synchronizer to sample the output of the C-bit counter synchronously with an output of one of the plurality of delay elements.
6. The digital fractional-N phase locked loop of claim 1 , wherein the ring phase calculator comprises a counter that counts dual-mode ring oscillator cycles and rolls over without being reset, a phase decoder to measure the counter's quantization error to a resolution of a fraction of a digital controlled oscillator cycle, and a clipper to reduce the worst-case locking time of the phase locked loop.
7. The digital fractional-N phase locked loop of claim 1 , wherein the ring phase calculator generates an output y[n] that is equivalent to a result of counting dual-mode ring oscillator cycles with an infinite-range counter, sampling the counter on each rising edge of a clock, and subtracting M times n from the result, where n=1, 2, 3, . . . .
8. The digital fractional-N phase locked loop of claim 7 , wherein M is a positive integer.
9. The digital fractional-N phase locked loop of claim 1 , wherein the local feedback path through the divider ensures that a rising edge of a reference applied to the input to the phase-frequency detector is followed by a rising edge of the divider output.
10. The digital fractional-N phase locked loop of claim 1 , wherein outputs of the dual-mode ring oscillator are sampled by the ring phase calculator at a frequency of a reference signal applied to the input of the phase-frequency detector.
11. The digital fractional-N phase locked loop of claim 10 , wherein the ring phase calculator samples the outputs of the dual-mode ring oscillator on a falling edge of the reference signal applied to the input when a frequency of the dual-mode ring oscillator is low.
12. The digital fractional-N phase locked loop of claim 1 , wherein the dual-mode ring oscillator operates at a high frequency in response to a rising edge of a reference signal applied to an input of the phase-frequency detector and operates at a low frequency in response to a rising edge of the divider output signal applied to an input of the phase-frequency detector.
13. The digital fractional-N phase locked loop of claim 1 , wherein the phase-frequency detector is configured such that its output is high only when a reference signal applied to one of its inputs is high.
14. The digital fractional-N phase locked loop of claim 1 , wherein the digital linear filter comprises a 2−z −1 digital filter.