Silicon carbide device and method of making thereof

1. A silicon carbide (SiC) device, comprising:

a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises:

a drift region having a first conductivity type;

a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and

a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×10 14 cm −2 , and wherein the pinch region depletes at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region, wherein the nominal current density is a rated current density of the SiC device, and wherein the well region is doped about two times (2×) to about fifteen times (15×) greater than the pinch region.

2. The SiC device of claim 1 , wherein the source contact region is at least about four times (4×) more heavily doped than the pinch region.

3. The SiC device of claim 1 , wherein the pinch region substantially increases the resistance of the SiC device when the current density is at least about four times (4×) greater than the nominal current density of the SiC device.

4. The SiC device of claim 1 , wherein the sheet doping density in the pinch region is between approximately 2.5×10 12 cm′ and approximately 5×10 13 cm −2 .

5. The SiC device of claim 1 , the width of the pinch region is between approximately 0.5 micrometers and approximately 2.5 micrometers, and wherein the pinch region provides a short-circuit withstand time between approximately 5 microseconds and 20 microseconds when supporting greater than 30 percent of rated drain-source voltage.

6. The SiC device of claim 1 , wherein the peak current is limited to about four times (4×) to about ten times (10×) of a rated current of the SiC device under short-circuit faults with drain voltages of greater than 30 percent of a rated voltage of the SiC device.

7. The SiC device of claim 1 , wherein the nominal current density is approximately 200 A/cm 2 .

8. The SiC device of claim 1 , wherein the device has a vertical device structure comprising a source/body contact disposed above the SiC semiconductor layer and a drain contact disposed below the SiC semiconductor layer.

9. The SiC device of claim 1 , wherein a portion of the well region disposed adjacent the surface of the SiC semiconductor layer and below the gate electrode forms a channel region having the second conductivity-type.

10. A silicon carbide (SiC) device, comprising:

a plurality of semiconductor device cells, wherein each of the plurality of semiconductor device cells comprises:

a drift region having a first conductivity type;

a gate electrode disposed above the drift region;

a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and

a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is not completely disposed below the gate electrode, wherein a sheet doping density in the pinch region is substantially less than 2.5×10 14 cm −2 and a sheet doping density in the source contact region is at least 2.5×10 14 cm −2 , and wherein the well region is doped about two times (2×) to about fifteen times (15×) greater than the pinch region.

11. The SiC device of claim 10 , wherein the pinch region depletes at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region, wherein the nominal current density is a rated current density of the SiC device.

12. The SiC device of claim 10 , wherein the semiconductor layer is included in a device comprising a MOSFET, UMOSFET, VMOSFETs, insulated gate bipolar transistors (IGBT), insulated base MOS-controlled thyristors (IBMCT), junction field effect transistors (JFET), or metal-semiconductor field effect transistor (MESFET).

13. The SiC device of claim 10 , wherein the pinch region substantially increases the resistance of the SiC device when a current density is at least about four times (4×) greater than a nominal current density of the SiC device, wherein the nominal current density is a rated current density of the SiC device.

14. The SiC device of claim 10 , wherein the sheet doping density in the pinch region is between approximately 2.5×10 12 cm′ and approximately 5×10 13 cm −2 and the dopant concentration in the source contact region is between approximately 1×10 15 cm −2 and approximately 8×10 15 cm −2 .

15. The SiC device of claim 10 , wherein the width of the pinch region is between approximately 0.5 micrometers and approximately 2.5 micrometers.

16. The SiC device of claim 10 , wherein the sheet doping density concentration of the pinch region times the length of the pinch region is from approximately 1.25×10 8 cm −1 to 125×10 8 cm −1 .

17. The SiC device of claim 10 , wherein the pinch region provides near constant drain current versus drain voltage dependence.

18. A method of fabricating a silicon carbide (SiC) semiconductor layer, comprising:

forming a source region having a first conductivity type, comprising:

implanting a pinch region of the source region to a sheet doping density of substantially less than 2.5×10 14 cm −2 ; and

implanting a source contact region of the source region adjacent to the pinch region to a sheet doping density higher than that of the pinch region;

forming a well region having a second conductivity type adjacent to the source region by implanting the well region to a sheet doping density that is about two times (2×) to about fifteen times (15×) higher than that of the pinch region; and

forming a gate electrode above a portion of the pinch region and a portion of the well region, wherein the gate electrode does not completely cover the pinch region of the source region.

19. The method of claim 18 , wherein implanting the source contact region comprises implanting the source contact region to a sheet doping density of at least about four times (4×) greater than the sheet doping density of the pinch region.

20. The method of claim 19 , comprising implanting the pinch region to a sheet doping density between approximately 2.5×10 12 cm −2 and approximately 5×10 13 cm −2 .