System and method for contextual vectorization of instructions at runtime
Methods and apparatuses relating to processors that contextually optimize instructions at runtime are disclosed. In one embodiment, a processors includes a fetch circuit to fetch an instruction from an instruction storage, a format of the instruction including an opcode, a first source operand identifier, and a second source operand identifier; wherein the instruction storage includes a sequence of sub-optimal instructions preceded by a start-of-sequence instruction and followed by an end-of-sequence instruction. The disclosed processor further includes a decode circuit to decode the instruction, to detect the start-of-sequence instruction and the end-of-sequence instruction, to buffer the sequence of sub-optimal instructions there between, to access a lookup table to identify one or more optimized instructions to substitute for one or more of the sequence of sub-optimal instructions, and to select either the decoded instruction or the sequence of one or more optimized instructions to dispatch to an execution circuit.
1. A processor to optimize instructions at run-time, comprising:
fetch and decode circuitry to fetch and decode the instructions;
an instruction buffer comprising at least four entries to buffer decoded instructions;
a substitute evaluation circuit to operate during run-time to:
determine whether an operating mode is an optimize mode;
identify, among the buffered instructions, a sequence of sub-optimal instructions comprising three or more instructions and delimited by a start-of-sequence instruction;
access processor contextual data, including contents of a register file;
access a lookup table of substitute instructions; and
select, for each of the buffered instructions, between the buffered instruction and one or more substitute instructions based on the operating mode, the sequence of sub-optimal instructions, the processor contextual data, and the contents of the lookup table; and
an execution circuit to execute the each of the selected instructions.
2. The processor of claim 1 , wherein the sequence of sub-optimal instructions are sub-optimal because they use an older generation of an instruction set architecture (ISA) than the instructions in the lookup table.
3. The processor of claim 1 , wherein the sequence of sub-optimal instructions are sub-optimal because they include vector instructions written to use smaller vector registers than are available on the processor.
4. The processor of claim 1 , wherein the sequence of sub-optimal instructions include scalar multimedia operations and the substitute instructions include vector instructions.
5. The processor of claim 1 , wherein the sequence of sub-optimal instructions are sub-optimal because the processor contextual data indicates that the sub-optimal instructions are using more than one memory access to access a same cache line.
6. The processor of claim 1 , wherein the buffered instructions comprise scalar instructions and a sequence of one or more optimized instructions comprises vector instructions.
7. The processor of claim 1 , wherein the buffered instructions comprise scalar instructions and a sequence of one or more optimized instructions comprises SIMD instructions.
8. The processor of claim 1 , further comprising an optimize mode detector circuit to monitor the instruction buffer at runtime, set the optimize mode to TRUE when the start-of-sequence instruction is detected, and set the optimize mode to FALSE when an end-of-sequence instruction is detected.
9. The processor of claim 8 , wherein the start-of-sequence instruction includes metadata to provide hints on whether and how to perform substituting.
10. A method of optimizing instructions by a processor at run-time, comprising:
determining, by a substitute evaluation circuit, that the processor is running in an optimize mode;
fetching and decoding the instructions using fetch circuitry and decode circuitry;
buffering decoded instructions in an instruction buffer comprising at least four entries;
identifying, by the substitute evaluation circuit, a sequence of sub-optimal instructions comprising three or more instructions delimited by a start-of-sequence instruction;
accessing, by the substitute evaluation circuit, processor contextual data, including contents of a register file;
accessing by the substitute evaluation circuit, a lookup table of substitute instructions;
for each buffered instruction, selecting, based on the sequence of sub-optimal instructions, the processor contextual data, and the contents of the lookup table, between the buffered instruction and substitute one or more substitute instructions; and
executing, by an execution circuit, the selected instructions.
11. The method of claim 10 , wherein the sequence of sub-optimal instructions are sub-optimal because they use an older generation of an instruction set architecture (ISA) than the instructions in the lookup table.
12. The method of claim 10 , wherein the sequence of sub-optimal instructions are sub-optimal because they include vector instructions written to use smaller vector registers than are available on a processor.
13. The method of claim 10 , wherein the sequence of sub-optimal instructions include scalar multimedia operations and the substitute instructions include vector instructions.
14. The method of claim 10 , wherein the sequence of sub-optimal instructions are sub-optimal because, according to the processor contextual data, they are using more than one memory access to access a same cache line.
15. The method of claim 10 , wherein the buffered instructions comprises scalar instructions and a sequence of one or more optimized instructions comprises SIMD instructions.
16. The method of claim 10 , wherein the start-of-sequence instruction includes metadata to provide hints on whether and how to perform substituting.
17. A non-transitory machine-readable medium containing instructions that, when executed by a processor, cause the processor to optimize instructions at run-time by:
determining that the processor is running in an optimize mode;
fetching and decoding the instructions using fetch circuitry and decode circuitry;
buffering decoded instructions in an instruction buffer comprising at least four entries;
identifying a sequence of sub-optimal instructions comprising three or more of the buffered instructions delimited by a start-of-sequence instruction;
accessing processor contextual data, including contents of a register file;
accessing a lookup table of substitute instructions;
for each buffered instruction, selecting, based on the sequence of sub-optimal instructions, the processor contextual data, and the contents of the lookup table, between the buffered instruction and one or more substitute instructions; and
an execution circuit to execute the selected instructions.
18. The non-transitory machine-readable medium of claim 17 , wherein the sequence of sub-optimal instructions include scalar instructions and the substitute instructions include vector instructions.
19. The non-transitory machine-readable medium of claim 17 , wherein the one or more buffered instructions comprises scalar instructions and a sequence of one or more optimized instructions comprises SIMD instructions.
20. The non-transitory machine-readable medium of claim 17 , wherein the start-of-sequence instruction includes metadata to provide hints on whether and how to perform substituting.