Systems and methods for using alternate computer instruction sets
Systems and methods for using alternate computer instruction sets are disclosed. In one embodiment, a method of program execution using an alternate instruction set may include (1) enabling a computer processor to use an alternate instruction set; (2) a first computer program in memory issuing a first instruction for execution by the computer processor; (3) the computer processor determining that the first instruction issued by the first computer program is in the alternate instruction set; (4) the computer processor translating the first instruction issued by the first computer program; and (5) the computer processor executing the translated instruction.
1. A method for program execution using an alternate instruction set, comprising:
enabling a computer processor to use an alternate instruction set, wherein each instruction in the alternate instruction set maps to a standard instruction for the computer processor;
a first computer program in memory issuing a first instruction for execution by the computer processor;
the computer processor determining that the first instruction issued by the first computer program is in the alternate instruction set;
the computer processor translating the first instruction issued by the first computer program into the mapped standard instruction for the computer processor; and
the computer processor executing the mapped standard instruction.
2. The method of claim 1 , wherein a binary machine code disassembler disassembles the alternate instruction into assembly code, and the translated instruction comprises the assembly code.
3. The method of claim 1 , wherein the step of enabling a computer processor to use an alternate instruction set comprises:
an operating system bootloader loading the alternate instruction set to a memory.
4. The method of claim 3 , wherein the memory is internal to the computer processor.
5. The method of claim 1 , wherein a translation look-aside buffer translates the first instruction issued by the first computer program.
6. The method of claim 1 , wherein the alternate instruction set comprises instructions have a different format from a standard instruction for the computer processor.
7. The method of claim 1 , wherein the alternate instruction set instruction are executed in a different processor mode than a standard instruction for the computer processor.
8. The method of claim 1 , wherein the alternate instruction set instruction are executed in a different address mode than a standard instruction set for the computer processor.
9. The method of claim 1 , further comprising:
the computer processor compiling the first computer program for the alternate instruction set.
10. The method of claim 9 , further comprising:
a second computer program in memory issuing a second instruction for execution by the computer processor;
the computer processor determining that the second instruction issued by the computer program is not in the alternate instruction set; and
the computer processor preventing the second instruction from executing.
11. The method of claim 10 , further comprising:
the computer processor executing a no operation in response to the second instruction not being in the alternate instruction set.
12. The method of claim 9 , wherein the computer processor generates an exception in response to the second instruction not being in the alternate instruction set.
13. The method of claim 9 , wherein the computer processor restarts the computer in response to the second instruction not being in the alternate instruction set.
14. A method for program execution using an alternate instruction set, comprising:
enabling a computer processor to use an alternate instruction set, wherein each instruction in the alternate instruction set maps to a standard instruction for the computer processor;
a computer program in memory issuing an instruction for execution by the computer processor;
the computer processor determining that the instruction issued by the computer program is not in the alternate instruction set; and
the computer processor preventing the instruction from executing.
15. The method of claim 14 , further comprising:
the computer processor executing a no operation in response to the second instruction not being in the alternate instruction set.
16. The method of claim 14 , wherein the computer processor generates an exception in response to the second instruction not being in the alternate instruction set.
17. The method of claim 14 , wherein the computer processor causes a computer associated with the computer processor to restart in response to the second instruction not being in the alternate instruction set.
18. The method of claim 14 , wherein the computer processor enables a second alternate instruction set in response to the second instruction not being in the alternate instruction set.
19. The method of claim 14 , wherein the computer processor changes a computer processor mode in response to the second instruction not being in the alternate instruction set.
20. The method of claim 1 , wherein the instructions in the alternate instruction set are randomly mapped to the standard instructions for the computer processor.