COST EFFECTIVE MULTIBAND RF FRONT-END ARCHITECTURE FOR MOBILE APPLICATIONS
One embodiment of the present invention provides an RF front-end system. The RF front-end system includes one or more RF front-end components and a programmable logic device, which has a baseband interface for coupling to a baseband digital signal processor (DSP), and a set of component interfaces for coupling to the one ore more RF front-end components. The programmable logic device is configured to: receive, from the baseband DSP via the baseband interface, a command which includes an address and a control signal; identify a component interface from the set of component interfaces based on the address; and send the control signal to the identified component interface, thereby enabling the baseband DSP to control a front-end component coupled to the programmable logic device via the identified component interface.
1 . An RF front-end system, comprising:
one or more RF front-end components; and
a programmable logic device having a baseband interface and a set of component interfaces, wherein a respective component interface is coupled to an RF front-end component and mapped to an address identifiable by the programmable logic device;
wherein the programmable logic device is configured to:
receive, from the baseband DSP via the baseband interface, a command, wherein the command specifies an address and includes a control signal;
identify a component interface from the set of component interfaces based on the address specified by the command; and
send the control signal to the identified component interface, thereby enabling the baseband DSP to control a corresponding RF front-end component coupled to the programmable logic device via the identified component interface.
2 . The RF front-end system of claim 1 , wherein the baseband interface includes one of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
3 . The RF front-end system of claim 1 , wherein the programmable logic device includes at least one of:
a complex programmable logic device (CPLD);
a field-programmable gate array (FPGA); and
a programmable logic device (PLA).
4 . The RF front-end system of claim 1 , wherein the set of component interfaces include one or more of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
5 . The RF front-end system of claim 1 , wherein the command includes at least one of: a write command and a read command.
6 . The RF front-end system of claim 5 , wherein the programmable logic device is further configured to:
in response to the read command, obtain a status reading from the identified component interface for the corresponding RF front-end component; and
send the status reading to the baseband DSP via the baseband interface.
7 . The RF front-end system of claim 1 , wherein the RF front-end components include one or more of:
one or more of integrated circuit (IC) chips;
a power management unit;
an antenna tuner;
a filter;
a band-selection switch;
an operation mode switch configured to switch between a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
a power amplifier;
a low-noise amplifier;
a power detector; and
an automatic gain control (AGC) circuitry.
8 . The RF front-end system of claim 7 , wherein the IC chips includes at least one transceiver IC chip.
9 . The RF front-end system of claim 1 , wherein the programmable logic device further comprises an additional baseband interface to enable a slow write/read operation between the baseband DSP and the programmable logic device.
10 . The RF front-end system of claim 1 , further comprising an RF IC chip situated between the baseband DSP and the programmable logic device, wherein the RF IC chip is configured to:
receive, from the baseband DSP, a second command;
determine whether a second address included in the second command is within a predetermined range; and
in response to determining the second address being outside of the predetermined range, forward the second command to the programmable logic device.
11 . The RF front-end system of claim 10 , wherein the RF IC chip is further configured to:
in response to determining the second address being within the predetermined range, identifying an RF IC component within the RF IC chip based on the second address; and
forward a control signal within the second command to the identified RF IC component.
12 . A method for controlling a plurality of RF front-end components of a wireless transceiver, comprising:
coupling the plurality of RF front-end components to a programmable logic device via a set of component interfaces;
coupling the programmable logic device to a baseband DSP of the wireless transceiver via a baseband interface;
receiving, by a programmable logic device via the baseband interface, a command sent from the baseband DSP, wherein the command specifies an address identifiable by the programmable logic device and includes a control signal for controlling operations of an RF front-end component;
identifying a component interface from the set of component interfaces based on the address specified by the command; and
sending the control signal to the RF front-end component via the identified component interface.
13 . The method of claim 12 , wherein the baseband interface includes one of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
14 . The method of claim 12 , wherein the programmable logic device includes at least one of:
a complex programmable logic device (CPLD);
a field-programmable gate array (FPGA); and
a programmable logic device (PLA).
15 . The method of claim 12 , wherein the set of component interfaces include one or more of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
16 . The method of claim 12 , wherein the command includes at least one of: a write command and a read command.
17 . The method of claim 16 , further comprising:
in response to receiving the read command from the baseband DSP, obtaining a status reading from the identified component interface for the RF front-end component; and
sending the status reading to the baseband DSP via the baseband interface.
18 . The method of claim 12 , wherein the RF front-end components include one or more of:
one or more of integrated circuit (IC) chips;
a power management unit;
an antenna tuner;
a filter;
a band-selection switch;
an operation mode switch configured to switch between a time division duplex (TDD) mode and a frequency division duplex (FDD) mode;
a power amplifier;
a low-noise amplifier;
a power detector; and
an automatic gain control (AGC) circuitry.
19 . The method of claim 18 , wherein the IC chips includes at least one transceiver IC chip.
20 . The method of claim 12 , wherein the programmable logic device further comprises an additional baseband interface to enable a slow write/read operation between the baseband DSP and the programmable logic device.
21 . The method of claim 12 , wherein the programmable logic device is coupled to the baseband DSP via an RF IC chip, wherein the RF IC chip is configured to:
receive, from the baseband DSP, a second command specifying a second address;
determine whether the second address is within a predetermined range; and
in response to determining the second address being outside of the predetermined range, forward the second command to the programmable logic device.
22 . The method of claim 21 , wherein the RF IC chip is further configured to:
in response to determining the second address being within the predetermined range, identifying an RF IC component within the RF IC chip based on the second address; and
forward a control signal within the second command to the identified RF IC component.