Surface devices within a vertical power device

1. A semiconductor device comprising:

a vertical power device that is electrically active along a vertical axis of the semiconductor device and that has at least one primary electrical terminal on the back surface of the semiconductor device;

a surface device comprising one or more lateral devices that are electrically active along a top surface of the semiconductor device; and,

wherein the surface device is configured to control the vertical power device.

2. The semiconductor device of claim 1 :

wherein the vertical power device forms a superjunction metal oxide semiconductor field effect transistor (SJMOSFET).

3. The semiconductor device of claim 1 :

wherein the vertical power device is comprised of a superjunction metal oxide semiconductor field effect transistor (SJMOSFET) and an insulated-gate bipolar transistor (IGBT).

4. The semiconductor device of claim 1 :

wherein the vertical power device is comprised of a superjunction metal oxide semiconductor field effect transistor (SJMOSFET), an insulated-gate bipolar transistor (IGBT), and a power diode.

5. The semiconductor device of claim 2 :

wherein the one or more lateral devices include one or more of an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, a Lateral-Drift MOS (LDMOS) transistor, an NPN bipolar junction transistor (NPN), a PNP bipolar junction transistor (PNP), a floating-gate MOS transistor, a diode, a resistor, a capacitor, an inductor, and a fusible element.

6. The semiconductor device of claim 2 :

wherein the one or more lateral devices are interconnected to form one or more of an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a state machine, an analog to digital converter, a digital to analog converter, a gate driver, a temperature sensor, a logic gate, a processor, and any other mixed analog-digital circuit construct.

7. The semiconductor device of claim 5 :

wherein the surface device comprises a medium voltage region and a low voltage region;

wherein the medium voltage region comprises an NMOS region and a PMOS region; and,

wherein the low voltage region comprises an NMOS region and a PMOS region.

8. The semiconductor device of claim 1 , further comprising:

a metal layer on a top side of the semiconductor device; and,

wherein the metal layer interconnects the vertical power device to the surface device.

9. The semiconductor device of claim 1 :

wherein portions of the surface device are interspersed with portions of the vertical power device to dissipate heat from the vertical power device and lower an overall temperature of the semiconductor device.

10. The semiconductor device of claim 8 further comprising:

an insulator separating the vertical power device from the surface device; and,

wherein the semiconductor device is formed as a silicon-on-insulator device and the insulator is one of silicon oxide and aluminum oxide.

11. A semiconductor device comprising:

a vertical power device that is electrically active along a vertical axis of the semiconductor device and forms an insulated gate bipolar transistor (IGBT) that has a collector terminal on the back surface of the semiconductor device;

a surface device comprising one or more lateral devices that are electrically active along a top surface of the semiconductor device; and,

wherein the surface device is configured to control the vertical power device.

12. The semiconductor device of claim 11 :

wherein the one or more lateral devices include one or more of an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, a Lateral-Drift MOS (LDMOS) transistor, an NPN bipolar junction transistor (NPN), a PNP bipolar junction transistor (PNP), a floating-gate MOS transistor, a diode, a resistor, a capacitor, an inductor, and a fusible element.

13. The semiconductor device of claim 11 :

wherein the one or more lateral devices are interconnected to form one or more of an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a state machine, an analog to digital converter, a digital to analog converter, a gate driver, a temperature sensor, a logic gate, a processor, and any other mixed analog-digital circuit construct.

14. The semiconductor device of claim 11 :

wherein the surface device comprises a medium voltage region and a low voltage region;

wherein the medium voltage region comprises an NMOS region and a PMOS region; and,

wherein the low voltage region comprises an NMOS region and a PMOS region.

15. The semiconductor device of claim 11 , further comprising:

a metal layer on a top side of the semiconductor device; and,

wherein the metal layer interconnects the vertical power device to the surface device.

16. The semiconductor device of claim 11 :

wherein portions of the surface device are interspersed with portions of the vertical power device to dissipate heat from the vertical power device and lower an overall temperature of the semiconductor device.

17. The semiconductor device of claim 11 further comprising:

an insulator separating the vertical power device from the surface device; and,

wherein the semiconductor device is formed as a silicon-on-insulator device and the insulator is one of silicon oxide and aluminum oxide.

18. A semiconductor device comprising:

a vertical power device that is electrically active along a vertical axis of the semiconductor device and forms a diode that has a cathode terminal on the back surface of the semiconductor device;

a surface device comprising one or more lateral devices that are electrically active along a top surface of the semiconductor device; and,

wherein the surface device is configured to control the vertical power device.

19. The semiconductor device of claim 18 :

wherein the one or more lateral devices include one or more of an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, a Lateral-Drift MOS (LDMOS) transistor, an NPN bipolar junction transistor (NPN), a PNP bipolar junction transistor (PNP), a floating-gate MOS transistor, a diode, a resistor, a capacitor, an inductor, and a fusible element; and,

wherein the one or more lateral devices are interconnected to form one or more of an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a state machine, an analog to digital converter, a digital to analog converter, a gate driver, a temperature sensor, a logic gate, a processor, and any other mixed analog-digital circuit construct.

20. The semiconductor device of claim 18 :

wherein the surface device comprises a medium voltage region and a low voltage region;

wherein the medium voltage region comprises an NMOS region and a PMOS region; and,

wherein the low voltage region comprises an NMOS region and a PMOS region.

21. The semiconductor device of claim 18 , further comprising:

an insulator separating the vertical power device from the surface device; and,

wherein the semiconductor device is formed as a silicon-on-insulator device and the insulator is one of silicon oxide and aluminum oxide.

22. A semiconductor device comprising:

a vertical power device that is electrically active along a vertical axis of the semiconductor device and that has at least one primary electrical terminal on the back surface of the semiconductor device;

a surface device comprising one or more lateral devices that are electrically active along a top surface of the semiconductor device;

wherein the one or more lateral devices include one or more of an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, a Lateral-Drift MOS (LDMOS) transistor, an NPN bipolar junction transistor (NPN), a PNP bipolar junction transistor (PNP), a floating-gate MOS transistor, a diode, a resistor, a capacitor, an inductor, and a fusible element; and,

wherein the surface device is configured to control the vertical power device.

23. The semiconductor device of claim 22 :

wherein the vertical power device forms a superjunction metal oxide semiconductor field effect transistor (SJMOSFET).

24. The semiconductor device of claim 22 :

wherein the vertical power device is comprised of a superjunction metal oxide semiconductor field effect transistor (SJMOSFET) and an insulated-gate bipolar transistor (IGBT).

25. The semiconductor device of claim 22 :

wherein the vertical power device is comprised of a superjunction metal oxide semiconductor field effect transistor (SJMOSFET), an insulated-gate bipolar transistor (IGBT), and a power diode.

26. The semiconductor device of claim 22 , further comprising:

a metal layer on a top side of the semiconductor device; and,

wherein the metal layer interconnects the vertical power device to the surface device.

27. The semiconductor device of claim 26 further comprising:

an insulator separating the vertical power device from the surface device; and,

wherein the semiconductor device is formed as a silicon-on-insulator device and the insulator is one of silicon oxide and aluminum oxide.