Tester for integrated circuits on a silicon wafer and integrated circuit
A tester for integrated circuits on a silicon wafer includes an input/output connection for testing an integrated circuit. The tester comprises circuitry arranged for transferring a first data frame to the integrated circuit via the input/output connection, the first data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one test command and for receiving a second data frame via the input/output connection, the data in the second data frame received having a duration that is a multiple of the time reference.
1. A tester for integrated circuits on a silicon wafer, wherein the tester comprises:
a single input/output connection for testing an integrated circuit; and
circuitry causing the tester to perform:
transferring a first data frame to the integrated circuit via the input/output connection, the first data frame comprising (1) a field that is a time reference for data included in the first data frame, (2) a field for validating the time reference being a multiple of a duration of the field that is a time reference, and (3) a data field comprising at least one test command; and
receiving, from an integrated circuit on the silicon wafer, a second data frame via the input/output connection, data in the second data frame being received within a duration equal to an integer number that is a multiple of the time reference and greater than or equal to twice the time reference.
2. The tester according to claim 1 , wherein the data in the second data frame is received within a duration equal to an integer number that is a multiple of twice of the time reference.
3. The tester according to claim 1 , wherein each data in the first data frame transferred to the integrated circuit is represented by a logic high and low level.
4. The tester according to claim 1 , wherein the data frame transferred to the integrated circuit further comprises a value associated with the at least one test command to test the integrated circuit.
5. The tester according to claim 1 , wherein the at least one test command to test the integrated circuit is for adjusting an analogue value, a frequency value, or a digital value in the integrated circuit.
6. The tester according to claim 5 , wherein the at least one test command is to transmit or receive an analogue signal in a time window following the first data frame and the tester comprises circuitry causing the tester to perform transmitting or receiving the analogue signal in the time window following the data frame.
7. The tester according to claim 5 , wherein the at least one test command is for adjusting an internal clock of the integrated circuit or for adjusting a voltage for writing or deleting a data item in a memory of the integrated circuit.
8. An integrated circuit comprising:
an input/output connection for testing the integrated circuit; and
circuitry causing the integrated circuit to perform:
receiving a first data frame via the input/output connection, the first data frame comprising (1) a field that is a time reference for data included in the first data frame, (2) a field for validating the time reference being a multiple of a duration of the field that is a time reference, and (3) a data field comprising at least one test command; and
transferring a second data frame via the input/output connection, data in the second data frame being transferred within a duration equal to an integer number that is a multiple of the time reference and greater than or equal to twice the time reference.
9. The integrated circuit according to claim 8 , wherein the data of the first data frame is received within a duration equal to an integer number that is a multiple of twice the time reference.
10. The integrated circuit according to claim 8 , wherein the first data frame further comprises a value associated with the at least one test command to test the integrated circuit.
11. The integrated circuit according to claim 10 , wherein the at least one test command is to adjust an analogue value, a frequency value, or a digital value in the integrated circuit.
12. The integrated circuit according to claim 10 , wherein the at least one test command is to transmit or receive an analogue signal in a time window following the first data frame and the integrated circuit comprises circuitry causing the integrated circuit to perform transmitting or receiving the analogue signal in the time window following the first data frame.
13. The integrated circuit according to claim 10 , wherein the at least one test command is for adjusting an internal clock of the integrated circuit.
14. The integrated circuit according to claim 10 , wherein the at least one test command is for adjusting a voltage for writing or deleting a data in a memory of the integrated circuit.
15. The integrated circuit according to claim 12 , wherein, when the at least one test command is used for adjusting a write or delete voltage is received, the integrated circuit controls reading means in a memory of the integrated circuit by means of a state machine for adjusting the write or delete voltage.
16. A test method, using a tester of integrated circuits on a silicon wafer, the tester comprising a single input/output connection for testing an integrated circuit, wherein said method causes the tester to perform:
transferring a first data frame to the integrated circuit via the input/output connection, the first data frame comprising (1) a field that is a time reference for data included in the first data frame, (2) a field for validating the time reference being a multiple of a duration of the field that is a time reference, and (3) a data field comprising at least one test command; and
receiving a second data frame via the input/output connection, data in the second data frame is received within a duration equal to an integer number that is a multiple of the time reference and greater than or equal to twice time reference.
17. The method according to claim 16 , wherein the data in the second data frame is received within a duration equal to an integer number that is a multiple of twice the time reference.
18. A method for testing an integrated circuit comprising a single input/output connection for testing the integrated circuit, wherein said method comprises:
receiving, by the integrated circuit, a first data frame via the input/output connection, the first data frame comprising (1) a field that is a time reference for data included in the first data frame, (2) a field for validating the time reference being a multiple of a duration of the field that is a time reference, and (3) a data field comprising at least one test command,
transferring, by the integrated circuit, a second data frame via the input/output connection, data in the second data frame being transferred within a duration equal to an integer number that is a multiple of twice the time reference.
19. The method according to claim 18 , wherein the data in the second data frame is received within a duration equal to an integer number that is a multiple of the time reference.