IP Library Granted Patent US 10,373,970
Granted Patent B2
US 10,373,970 · App. 15/058,921 · Granted Aug 6, 2019

Semiconductor device structures including staircase structures, and related methods and electronic systems

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Quick Facts
Patent No.
US 10,373,970
App. No.
15/058,921
Granted
Aug 6, 2019
Kind
B2
Abstract

A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of faulting semiconductor device structures, and electronic systems are also described.

Claims (32)

1. A semiconductor device structure, comprising:

a stack structure including stacked tiers comprising conductive structures and insulating structures in a vertically alternating arrangement with one another, the stack structure comprising:

a stadium structure comprising:

a forward staircase structure having first steps comprising first horizontal ends of the stacked tiers; and

a reverse staircase structure mirroring the forward staircase structure and having second steps comprising second horizontal ends of the stacked tiers;

a middle section neighboring the stadium structure in a first horizontal direction and continuously extending from a top of the forward staircase structure to an opposing top of the reverse staircase structure in a second horizontal direction; and

opposing end sections integral and continuous with the stadium structure and the middle section; and

an opening vertically extending completely through the stack structure, the opening intervening between the stadium structure and the middle section in the first horizontal direction and extending from and between the opposing end sections in the second horizontal direction, each of the stacked tiers of the stack structure individually exhibiting one of the conductive structures extending continuously around the opening from the forward staircase structure, across each of a first of the opposing end sections, the middle section, and a second of the opposing end sections, and to the reverse staircase structure.

2. The semiconductor device structure of claim 1 , further comprising:

at least one contact structure coupled to one or more of the conductive structures of the stacked tiers at one or more of the forward staircase structure of the stadium structure and the reverse staircase structure of the stadium structure; and

at least one routing structure coupled to the at least one contact structure and extending to at least one switching device.

3. The semiconductor device structure of claim 1 , further comprising:

an additional stadium structure of the stack structure integral and continuous with the opposing end sections and separated from the stadium structure by the middle section, the additional stadium structure comprising:

an additional forward staircase structure having third steps comprising third horizontal ends of the stacked tiers; and

an additional reverse staircase structure mirroring the additional forward staircase structure and having fourth steps comprising fourth horizontal ends of the stacked tiers; and

an additional opening extending through the stack structure from the middle section to the additional stadium structure in the first horizontal direction and from and between the opposing end sections in the second direction, each of the stacked tiers of the stack structure individually exhibiting an additional conductive structure extending continuously around the additional opening from the additional forward staircase structure, across each of the first of the opposing end sections, the middle section, and the second of the opposing end sections, and to the additional reverse staircase structure.

4. The semiconductor device structure of claim 1 , wherein the middle section of the stack structure comprises additional insulating structures horizontally surrounded by portions of the conductive structures.

5. The semiconductor device structure of claim 4 , wherein each of the stacked tiers of the stack structure individually comprises:

one of the conductive structures;

one of the insulating structures vertically adjacent the one of the conductive structures; and

one of the additional insulating structures horizontally adjacent the one of the conductive structures.

6. The semiconductor device structure of claim 5 , wherein each of the stacked tiers of the stack structure individually further comprises another one of the conductive structures horizontally separated from the one of the conductive structures by the one of the additional insulating structures.

7. The semiconductor device structure of claim 1 , wherein boundaries of the opening are at least partially defined by each of an inner side surface of the middle section of the stack structure, an inner side surface of the stadium structure opposing the inner side surface of the middle section of the stack structure, and inner side surfaces of the opposing end sections of the stack structure.

8. The semiconductor device structure of claim 7 , wherein the conductive structures of the stacked tiers continuously follow along the inner side surface of the middle section of the stack structure, the inner side surface of the stadium structure, and the inner side surfaces of the opposing end sections of the stack structure.

9. An electronic system, comprising:

at least one semiconductor device structure comprising:

a stack structure including stacked tiers comprising conductive structures and insulating structures in a vertically alternating arrangement with one another, the stack structure comprising:

at least one stadium structure comprising opposing staircase structures having steps comprising horizontal ends of the stacked tiers;

a middle section neighboring the at least one stadium structure in a first horizontal direction and continuously extending from a top of a first of the opposing staircase structures to a top of a second of the opposing staircase structures in a second horizontal direction;

opposing end sections integral and continuous with the stadium structure and the middle section;

at least one opening vertically extending completely through the stack structure, the at least one opening intervening between the at least one stadium structure and the middle section in the first horizontal direction and extending from and between the opposing end sections in the second horizontal direction; and

continuous conductive paths at least partially formed by the conductive structures of the stacked tiers of the stack structure, each of the stacked tiers individually exhibiting one of the conductive structures extending continuously around the at least one opening from a first of the opposing staircase structures, across each of a first of the opposing end sections, the middle section, and a second of the opposing end sections, and to a second of the opposing staircase structures.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2016
From: LEE, ERIC N.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037874/0901 →