Interfacial cap for electrode contacts in memory cell arrays
View Patent ↗Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.
1. A method for fabricating a memory cell, the method comprising:
forming a contact via in a dielectric layer;
depositing a conductive material in the contact via;
removing a portion of the conductive material from the contact via;
depositing an interface cap material on a portion of the conductive material within the contact via to form an interface cap; and
depositing an active cell material on the interface cap,
wherein,
the interface cap is between the active cell material and the conductive material,
the interface cap is deposited in a recess which has a width greater than or equal to a height of the recess, and
the interface cap material has a resistivity that is less than a resistivity of a material forming the conductive material.
2. The method of claim 1 , further comprising:
modifying a resistance of the interface cap independently of the resistance of the conductive material in the contact via.
3. The method of claim 1 , further comprising:
performing chemical-mechanical planarization (CMP) on the conductive material in the contact via before forming the recess and before forming the interface cap in the recess; and
performing CMP on the interface cap material after deposition.
4. The method of claim 1 , wherein the interface cap material includes tungsten (W), and wherein the conductive material in the contact via includes TDMAT TiN.
5. The method of claim 1 , wherein the recess is approximately from 3 to 6 nm in height for a given diameter.
6. The method of claim 1 , wherein an aspect ratio of a depth of the recess to a diameter of the recess in a widest portion of the recess is less than one.
7. The method of claim 1 , further comprising:
depositing the interface cap material in the recess using physical vapor deposition or chemical vapor deposition (CVD).
8. The method of claim 7 further comprising:
depositing the conductive material in the contact via using CVD.
9. The method of claim 8 , further comprising:
forming the recess to a particular depth to eliminate a keyhole opening in the conductive material in the contact via.
10. The method of claim 1 , wherein the contact via is etched in the dielectric layer.
11. The method of claim 1 , wherein the conductive material in the contact via is approximately 40-70 nm in height.
12. The method of claim 1 , wherein the interface cap includes carbon.
13. The method of claim 1 , further comprising:
forming the interface cap with a higher energy of formation than the conductive material in the contact via.
14. The method of claim 1 , further comprising:
forming the interface cap so that the interface cap acts as an electromagnetic/diffusion barrier to elements included in at least one of the conductive material in the contact via and the active cell material.
15. The method of claim 1 , further comprising:
forming the interface cap using one of TDMAT TiN, TaN, WCN, or TiAlN.
16. The method of claim 1 , further comprising:
forming the interface cap on an etched portion of the conductive material within the contact via.
17. The method of claim 1 , further comprising:
forming the interface cap of a material that has a predetermined work function.
18. A device comprising:
a contact via in a dielectric layer;
a conductive material in the contact via;
an interfacial cap disposed on a portion of the conductive material within the contact via; and
an active cell material,
wherein,
the interfacial cap is between the active cell material and the conductive material,
the interfacial cap has a width greater than or equal to a height, and
the interfacial cap includes a material having a resistivity that is less than a resistivity of a material forming the conductive material.
19. The device of claim 18 , wherein the device forms a memory cell, and wherein the memory cell comprises one of phase-change memory, resistive ram (ReRAM), conductive-bridge RAM (CBRAM), or a logic gate.
20. The device of claim 18 , wherein the interfacial cap material is Tungsten (W) and the conductive material in the contact via is TDMAT TiN.
21. The device of claim 18 , wherein the interfacial cap material is Tungsten (W) and the conductive material in the contact via is CVD TiN.
22. The device of claim 21 , wherein the interfacial cap extends cycling endurance of the device because of the CVD TiN.
23. The device of claim 18 , wherein the interfacial cap includes a grain structure different from a grain structure of the conductive material in the contact via.
24. The device of claim 18 , wherein the interfacial cap includes carbon.
25. The device of claim 18 , wherein the interfacial cap has a higher energy of formation than the conductive material in the contact via.
26. The device of claim 18 , wherein the interfacial cap includes one of TDMAT TiN (TiCN), Tantalum Nitrogen (TaN), WCN or TiAlN.
27. The device of claim 18 , wherein a resistance of the conductive material in the contact via is engineered independently from a chemical and electronic interface of the active cell materials.
28. The device of claim 18 , wherein resistive heating is localized at the interfacial cap without increasing resistance in the conductive material in the contact via.
29. The device of claim 18 , wherein the interfacial cap is tailored to have a predetermined work function.
30. The device of claim 18 , wherein the interfacial cap is disposed on an etched portion of the conductive material within the contact via.
31. An electronic device comprising a plurality of memory tiles including an array of memory cells, each cell including:
a contact via in a dielectric layer;
a conductive material in the contact via;
an interfacial cap disposed on a portion of the conductive material within the contact via; and
an active cell material,
wherein,
the interfacial cap is between the active cell material and the conductive material,
the interfacial cap has a width greater than or equal to a height, and
the interfacial cap includes a material having a resistivity that is less than a resistivity of a material forming the conductive material.
32. The electronic device of claim 31 , wherein the interfacial cap is disposed on an etched portion of the conductive material within the contact via.