Memory control circuit, cache memory and memory control method

1. A memory control circuit comprising:

an error detector to detect whether an error is contained in data written in a first memory or data read from the first memory;

error correction circuitry to correct the error detected by the error detector;

first error determination circuitry to determine whether an error-bit number is larger than a first threshold value set based on a number less than a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that the error is contained in data read for verification of data written to the first memory or in data read from the first memory;

second error determination circuitry to determine whether the error-bit number is larger than a second threshold value set based on the maximum number of error bits, when it is determined that the error-bit number is larger than the first threshold value by the first error determination circuitry; and

an access controller to control whether data stored in the first memory is written to a second memory being accessed by a processor in lower priority than the first memory or the error correction circuitry corrects the error, based on results determined by the first error determination circuitry and the second error determination circuitry.

2. The memory control circuit of claim 1 , wherein the error determination circuitry reads data to verify the data when the data is written to the first memory, and determines whether the error-bit number is larger than the threshold value when it is detected by the error detector that the error is contained in the read data, and

when it is determined that the error-bit number is larger than the threshold value, the access controller writes data to be written in the first memory to the second memory in a write-through mode.

3. The memory control circuit of claim 1 , wherein the error determination circuitry determines whether the error-bit number is larger than the threshold value when it is detected by the error detector that the error is contained in data read from the first memory, and

when it is determined that the error-bit number is larger than the threshold value, and if the read data in the first memory is not written to the second memory, the access controller writes the data to the second memory.

4. The memory control circuit of claim 1 , wherein the threshold value is a value equal to or smaller than the maximum number of error bits.

5. The memory control circuit of claim 1 , wherein the error detector periodically detects whether the error is contained in a memory cell in the first memory, and,

for the memory cell in the first memory, the access controller periodically operates the error detector, the error correction circuitry, and the error determination circuitry, to control whether to write data stored in the first memory to the second memory.

6. A cache memory comprising:

a first memory that stores data;

an error detector to detect whether an error is contained in data written in the first memory or data read from the first memory;

error correction circuitry to correct the error detected by the error detector;

error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that the error is contained in data read for verification of data written to the first memory or in data read from the first memory; and

an access controller to control whether data stored in the first memory is written to a second memory being accessed by a processor in lower priority than the first memory or the error correction circuitry corrects the error, based on results determined by the error determination circuitry,

wherein the first memory comprises:

a plurality of MRAM (Magnetoresistive RAM) cells, each of which including a magnetoresistive element for data storage, and switchably capable of having a first resistance or a second resistance different from each other;

a reference cell having a resistance value between the first resistance value and the second resistance value; and

a data reader to determine a logic value of data read from the first memory based on a voltage difference between bit lines in a pair which are connected to a pair of the MRAM cells and in which a differential signal flows, when no error is detected by the error detector or when the error-bit number detected by the error detector is equal to or smaller than the threshold value, and determine the logic value of the data read from the first memory based on a result of comparison with the reference cell for each of the bit lines when the error-bit number detected by the error detector is larger than the threshold value,

wherein the error correction circuitry corrects the error based on data determined by the data reader based on the result of comparison with the reference cell for each of the bit lines when the error-bit number is larger than the threshold value, and

the access controller acquires data from the second memory when error correction by the error correction circuitry is impossible in a case where the error-bit number is larger than the threshold value.

7. A cache memory comprising:

a first memory that stores data;

an error detector to detect whether an error is contained in data written in the first memory or data read from the first memory;

error correction circuitry to correct the error detected by the error detector;

error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that the error is contained in data read for verification of data written to the first memory or in data read from the first memory;

an access controller to control whether data stored in the first memory is written to a second memory being accessed by a processor in lower priority than the first memory or the error correction circuitry corrects the error, based on results determined by the error determination circuitry;

hit determination circuitry to determine whether data of an access-requested address is stored in the first memory; and

first read-write determination circuitry to determine whether to write data to the first memory or read data, when the hit determination circuitry determines that the data is not stored in the first memory,

wherein, when the first read-write determination circuitry determines to read data, the access controller reads data of the corresponding address from the second memory and writes the data to the first memory, and when the first read-write determination circuitry determines to be write data to the first memory, the access controller writes data to be written to the first memory and reads data written in the first memory for verification, and sets a write-back mode if the error-bit number of the detected error is equal to or smaller than the threshold value, whereas sets a write-through mode to write the data to the first memory and the second memory if the error-bit number is larger than the threshold value.

8. The cache memory of claim 7 further comprising second read-write determination circuitry to determine whether to read data from or write data to the first memory, when the hit determination circuitry determines that the data is stored in the first memory,

wherein, when the second read-write determination circuitry determines to write data to the first memory, the access controller writes data to be written to the first memory and reads data written in the first memory for verification, and sets the write-back mode if the error-bit number of the detected error is equal to or smaller than the threshold value, whereas sets a write-through mode if the error-bit number is larger than the threshold value to write the data to the first memory and the second memory.

9. The cache memory of claim 8 , wherein, when the second read-write determination circuitry determines to read data from the first memory, the error determination circuitry reads data of an access-requested address from the first memory to determine whether there are error bits, and determines, when there are error bits, whether the error-bit number of the error bits is equal to or smaller than the threshold value, and

when the error determination circuitry determines that the error-bit number is equal to or smaller than the threshold value, the access controller transfers error-corrected data to the second memory and updates data in the first memory.

10. The cache memory of claim 9 , wherein, when it is determined that the error-bit number is larger than the threshold value, the error determination circuitry compares data in each of a plurality of memory cells in the first memory with a reference cell to identify data of a read-requested address and determines whether error correction is possible based on the identified data, and

when it is determined by the error determination circuitry that error correction is impossible, the access controller reads data of the corresponding address from the second memory, whereas, when it is determined that error correction is possible, the error correction circuitry performs error correction based on the identified data.