Memory device and method of operating the same

1. A memory device with a plurality of memory block, comprising:

memory blocks stacked on each other, wherein the memory blocks include memory cell strings having two or more select transistors and a plurality of memory cells, wherein the memory cells are coupled between the two or more select transistors,

wherein the memory cell strings are coupled to a plurality of common source lines, and

wherein the two or more select transistors included in the memory cell strings of the memory blocks have different threshold voltages from one another by applying different voltages to the common source lines respectively, applying a program voltage to a selected select line coupled to a gate of a selected select transistor among the select transistors, and applying pass voltages to unselected select lines.

2. The memory device of claim 1 , wherein the two or more select transistors of each memory block has a predetermined combination of threshold voltages.

3. The memory device of claim 2 , wherein each memory block is selected in response to the predetermined combination of voltages being applied to the two or more select transistors.

4. The memory device of claim 3 , wherein each memory block is selected when the two or more select transistors are turned on in response to the predetermined combination of voltages being applied to the two or more select transistors.

5. The memory device of claim 4 , wherein the two or more select transistors include two or more source select transistors having the predetermined combination of threshold voltages.

6. A memory device, comprising:

a first memory block including a first source select transistor, a second source select transistor, first memory cells, a first drain select transistor, and a second drain select transistor coupled in series between a first common source line and a bit line;

a second memory block disposed over the first memory block and including a third source select transistor, a fourth source select transistor, second memory cells, a third drain select transistor, and a fourth drain select transistor coupled in series between a second common source line and the bit line;

a peripheral circuit configured to program the first to fourth source select transistors; and

a control circuit configured to perform a program operation on the first to fourth source select transistors so that the first to fourth source select transistors have different threshold voltages from one another, and to control the peripheral circuit so that, when a program operation, a read operation or an erase operation is performed, the first memory block or the second memory block is electrically connected to the first common source line by applying a corresponding combination of voltages to a first source select line coupled in common to the first and third source select transistors and to a second source select line coupled in common to the second and fourth source select transistors.

7. The memory device of claim 6 , wherein the control circuit controls the peripheral circuit so that the second and fourth source select transistors are simultaneously programmed and the first and third source select transistors are simultaneously programmed.

8. The memory device of claim 7 , wherein the control circuit controls the peripheral circuit so that:

different voltages are applied to the first and second common source lines; and

a program voltage is applied to a source select line selected from the first and second source select lines and a pass voltage is applied to an unselected source select line.

9. The memory device of claim 6 , wherein the control circuit controls the peripheral circuit so that the first to fourth source select transistors are separately programmed.

10. The memory device of claim 9 , the control circuit controls the peripheral circuit so that:

a program permission voltage is applied to a common source line selected from the first and second common source lines, and a program inhibition voltage is applied to an unselected common source line; and

a program voltage is applied to a source select line selected from the first and second source select lines and a pass voltage is applied to an unselected source select line.

11. The memory device of claim 6 , further comprising:

a first dummy source select transistor coupled between the first common source line and the first source select transistor; and

a second dummy source select transistor coupled between the second common source line and the third source select transistor.

12. The memory device of claim 11 , wherein the first dummy source select transistor and the second dummy source select transistor have gates coupled in common to a dummy source select line.

13. The memory device of claim 12 , wherein the control circuit controls the peripheral circuit so that:

the first to fourth drain select transistors are programmed and have different threshold voltages;

a channel voltage of a memory block selected from the first and second memory blocks is decreased; and

a source select transistor selected between the first to fourth source select transistors is programmed.

14. The memory device of claim 13 , wherein, when the channel voltage of the memory block selected from the first and second memory blocks is decreased, the control circuit controls the peripheral circuit so that:

the bit line is discharged;

voltages to be applied to a first drain select line coupled in common to the first and third drain select transistors and to a second drain select line coupled in common to the second and fourth drain select transistors are adjusted so that the discharged bit line is electrically connected to a channel of the selected memory block;

a turn-off voltage is applied to the dummy source select line; and

the unselected memory block is isolated from the bit line.

15. The memory device of claim 14 , wherein, when the source select transistor selected between the first to fourth source select transistors is programmed, the control circuit controls the peripheral circuit so that a program voltage is applied to a source select line selected from the first and second source select lines, and a pass voltage is applied to an unselected source select line.

16. A method of operating a memory device, the method programming select transistors of memory blocks, comprising:

applying different voltages to common source lines respectively coupled to the memory blocks;

programming drain select transistors coupled between memory cells and a bit line;

decreasing a channel voltage of a memory block selected from the memory blocks; and

simultaneously programming source select transistors among the select transistors, wherein the source select transistors are included in the stacked memory blocks, are coupled between the memory cells and the common source lines, and are coupled to an identical source select line.

17. The method of claim 16 , wherein the different voltages applied to the common source lines are set such that:

a first voltage is applied to, among the common source lines, a common source line coupled to a memory block that includes a source select transistor to be programmed to have a first threshold voltage; and

a second voltage higher than the first voltage is applied to, among the common source lines, a common source line coupled to a memory block that includes a source select transistor to be programmed to have a second threshold voltage lower than the first threshold voltage.

18. The method of claim 16 , wherein decreasing the channel voltage of the selected memory block is performed by:

discharging the bit line;

isolating the selected memory block from a common source line coupled to the selected memory block; and

turning on drain select transistors included in the selected memory block.