SIMULATION DEVICE OF SEMICONDUCTOR DEVICE AND SIMULATION METHOD OF SEMICONDUCTOR DEVICE
A simulation device of a semiconductor device according to an embodiment is a simulation device for analyzing a structural defect of the semiconductor device, the semiconductor device having wiring lines disposed three-dimensionally therein, and the simulation device of the semiconductor device comprises: a correct structure acquiring unit that acquires a correct structure of the semiconductor device; a comparative structure acquiring unit that acquires a comparative structure, the comparative structure being a structure of the semiconductor device manufactured under a certain condition; a difference extracting unit that extracts a difference of the comparative structure with respect to the correct structure; and a defect determining unit that determines a defect of the comparative structure from the difference, the defect determining unit including an open/short attribute determining unit that determines whether the difference is an open attribute positioned inside the correct structure or a short attribute positioned outside the correct structure.
1 . A simulation device of a semiconductor device for analyzing a structural defect of the semiconductor device, the semiconductor device having a plurality of wiring lines disposed three-dimensionally therein, the simulation device of the semiconductor device comprising:
a correct structure acquiring unit that acquires a correct structure of the wiring lines of the semiconductor device;
a comparative structure acquiring unit that acquires a comparative structure, the comparative structure being a structure of the wiring lines of the semiconductor device manufactured under a certain condition;
a difference extracting unit that extracts a difference of the comparative structure with respect to the correct structure; and
a defect determining unit that determines a defect of the comparative structure from the difference,
the defect determining unit including an open/short attribute determining unit that determines whether the difference is an open attribute positioned inside the correct structure or a short attribute positioned outside the correct structure.
2 . The simulation device of the semiconductor device according to claim 1 , wherein
the defect determining unit determines the defect of the comparative structure for every partial difference, the partial difference being the difference divided into closed regions and further divided into being inside/outside the correct structure.
3 . The simulation device of the semiconductor device according to claim 1 , wherein
the defect determining unit includes a risk determining unit that determines a risk of an open defect or a short defect based on the difference.
4 . The simulation device of the semiconductor device according to claim 3 , wherein
the risk determining unit includes an intermediate structure acquiring unit that acquires an intermediate structure, the intermediate structure being a difference set of the difference subtracted from a sum-set of the correct structure and the comparative structure.
5 . The simulation device of the semiconductor device according to claim 4 , wherein
the risk determining unit includes a criticality determining unit that determines whether the difference contacts a plurality of electrically different wiring lines of the intermediate structure.
6 . The simulation device of the semiconductor device according to claim 4 , wherein
the risk determining unit includes a risk degree determining unit that determines whether an expanded difference being an outer periphery of the difference thickened by an amount of a certain value, contacts a plurality of electrically different wiring lines of the intermediate structure.
7 . The simulation device of the semiconductor device according to claim 6 , wherein
the certain value is calculated based on a process condition of the semiconductor device.
8 . The simulation device of the semiconductor device according to claim 6 , wherein
the certain value is a fixed value.
9 . The simulation device of the semiconductor device according to claim 6 , wherein
the risk determining unit, in the case that the difference is an open attribute positioned inside the correct structure, extracts the expanded difference being the outer periphery of the difference thickened by an amount of the certain value, only inside the correct structure.
10 . The simulation device of the semiconductor device according to claim 6 , wherein
the risk determining unit, in the case that the difference is a short attribute positioned outside the correct structure, extracts the expanded difference being the outer periphery of the difference thickened by an amount of the certain value, only outside the correct structure.
11 . A simulation method of a semiconductor device for analyzing a structural defect of the semiconductor device, the semiconductor device having a plurality of wiring lines disposed three-dimensionally therein, the simulation method of the semiconductor device comprising:
acquiring a correct structure of the wiring lines of the semiconductor device;
acquiring a comparative structure, the comparative structure being a structure of the wiring lines of the semiconductor device manufactured under a certain condition;
extracting a difference of the comparative structure with respect to the correct structure; and
determining a defect of the comparative structure from the difference,
when determining the defect of the comparative structure, determining whether the difference is an open attribute positioned inside the correct structure or a short attribute positioned outside the correct structure.
12 . The simulation method of the semiconductor device according to claim 11 , further comprising:
when determining the defect of the comparative structure, determining a risk of an open defect or a short defect based on the difference.
13 . The simulation method of the semiconductor device according to claim 12 , further comprising:
when determining the risk of the open defect or the short defect, acquiring an intermediate structure, the intermediate structure being a difference set of the difference subtracted from a sum-set of the correct structure and the comparative structure.
14 . The simulation method of the semiconductor device according to claim 13 , further comprising:
when acquiring the intermediate structure, determining whether the difference contacts a plurality of electrically different wiring lines of the intermediate structure.
15 . The simulation method of the semiconductor device according to claim 13 , further comprising:
when determining the risk of the open defect or the short defect, determining whether an expanded difference being an outer periphery of the difference thickened by an amount of a certain value, contacts a plurality of electrically different wiring lines of the intermediate structure.
16 . A simulation device of a semiconductor device for analyzing a structural defect of the semiconductor device, the semiconductor device having a plurality of wiring lines disposed three-dimensionally therein, the simulation device of the semiconductor device comprising:
a correct structure acquiring unit that acquires a correct structure of the wiring lines of the semiconductor device;
a structure-to-be-analyzed generating unit that generates a structure-to-be-analyzed being outer peripheries of the plurality of wiring lines of the correct structure thickened by an amount of a certain value; and
a defect determining unit that determines a defect by whether a plurality of electrically different fellow wiring lines of the structure-to-be-analyzed have an overlapping place.
17 . The simulation device of the semiconductor device according to claim 16 , wherein
the certain value is calculated based on a process condition of the semiconductor device.
18 . The simulation device of the semiconductor device according to claim 16 , wherein
the certain value is a fixed value.