Memory device that controls timing of receiving write data from a host
View Patent ↗A memory device includes a nonvolatile memory unit, a write buffer, and a controller. The controller is configured to receive a write command from a host, send a permission signal to the host after the write command is received, receive write data associated with a write command from the host in response to the permission signal, store the write data in the write buffer, and transfer the write data stored in the write buffer to the nonvolatile memory unit. The controller controls a timing of transmitting the permission signal, such that the write buffer is full for no longer than a predetermined length of time.
1. A memory system, comprising:
a nonvolatile memory;
a buffer memory; and
a controller configured to receive a write command from a host, send a permission signal to the host in response to receiving the write command, receive write data associated with the write command that the host sent in response to the permission signal, store the write data into the buffer memory, and transfer the write data stored in the buffer memory to the nonvolatile memory, wherein
the controller is configured to:
calculate a first timing at which the buffer memory will become full and a second timing at which space will become available in the buffer memory; and
control a timing of sending the permission signal on the basis of the first timing and the second timing, such that the buffer memory stays being full for no longer than a predetermined length of time due to the write data stored in the buffer memory.
2. The memory system according to claim 1 , wherein
the controller calculates the first timing on the basis of remaining space of the buffer memory and a data transfer speed of data from the host.
3. The memory system according to claim 1 , wherein the predetermined length of time is zero.
4. The memory system according to claim 1 , wherein
the controller is further configured to carry out a garbage collection operation to aggregate a plurality of fractions of valid data in the nonvolatile memory into a single fraction of valid data, and calculate the second timing on the basis of (i) a length of time taken to transfer write data stored in the buffer memory to the nonvolatile memory, (ii) a length of time taken to carry out the garbage collection operation, and (iii) a frequency ratio of the transfer of write data from the buffer memory to the nonvolatile memory with respect to transfer of valid data to the nonvolatile memory during the garbage collection operation.
5. The memory system according to claim 4 , wherein
the controller is further configured to control the buffer memory to have free space when the controller starts to carry out the garbage collection operation, and become substantially full when the controller ends the garbage collection operation and the transfer of write data from the buffer memory starts.
6. The memory system according to claim 1 , wherein
when the first timing is later than the second timing, the controller transmits the permission signal at a third timing, and
when the second timing is later than the first timing, the controller transmits the permission signal at a fourth timing that is later than the third timing.
7. The memory system according to claim 6 , wherein
when the second timing is later than the first timing, the controller communicates to the host a designated data size of write data that are allowed to be transmitted from the host together with the permission signal.
8. The memory system according to claim 7 , wherein
when the designated data size is smaller than a size of the write data corresponding to the write command, the controller transmits a second permission signal, after the controller receives write data of the designated data size and a sufficient space becomes available in the buffer memory.
9. The memory system according to claim 7 , wherein
the designated data size is greater than a unit size of space in the buffer memory that is released.
10. A storage system comprising:
a memory system; and
a host configured to access the memory system, wherein
the memory system includes:
a nonvolatile memory;
a buffer memory; and
a controller configured to receive a write command from the host, send a permission signal to the host in response to receiving the write command, receive write data associated with the write command that the host sends in response to the permission signal, store the write data into the buffer memory, and transfer the write data stored in the buffer memory to the nonvolatile memory, wherein
the controller is configured to:
calculate a first timing at which the buffer memory will become full and a second timing at which space will become available in the buffer memory; and
control a timing of sending the permission signal on the basis of the first timing and the second timing, such that the buffer memory stays being full for no longer than a predetermined length of time due to the write data stored in the buffer memory.
11. The storage system according to claim 10 , wherein
the controller calculates the first timing on the basis of remaining space of the buffer memory and a data transfer speed of data from the host.
12. The storage system according to claim 10 , wherein the predetermined length of time is zero.
13. The storage system according to claim 10 , wherein
the controller is further configured to carry out a garbage collection operation to aggregate a plurality of fractions of valid data in the nonvolatile memory into a single fraction of valid data, and calculates the second timing on the basis of (i) a length of time taken to transfer write data stored in the buffer memory to the nonvolatile memory, (ii) a length of time taken to carry out the garbage collection operation, and (iii) a frequency ratio of the transfer of write data from the buffer memory to the nonvolatile memory with respect to transfer of valid data to the nonvolatile memory during the garbage collection operation.
14. The storage system according to claim 13 , wherein
the controller is further configured to control the buffer memory to have free space when the controller starts to carry out the garbage collection operation, and become substantially full when the controller ends the garbage collection operation and the transfer of write data from the buffer memory starts.
15. The storage system according to claim 10 , wherein
when the first timing is later than the second timing, the controller transmits the permission signal at a third timing, and
when the second timing is later than the first timing, the controller transmits the permission signal at a fourth timing that is later than the third timing.
16. The storage system according to claim 15 , wherein
when the second timing is later than the first timing, the controller communicates to the host a designated data size of write data that are allowed to be transmitted from the host together with the permission signal.
17. The storage system according to claim 16 , wherein
when the designated data size is smaller than a size of the write data corresponding to the write command, the controller transmits a second permission signal, after the controller receives write data of the designated data size and a sufficient space becomes available in the buffer memory.
18. The storage system according to claim 16 , wherein
the designated data size is greater than a unit size of space in the buffer memory that is released.