Read latency reduction in a memory device
View Patent ↗A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
1. A memory device, comprising:
a) a memory array comprising a plurality of memory cells arranged as a plurality of data lines, wherein each data line comprises a predetermined number of bytes of data;
b) an interface configured to receive a read command from a host that requests a plurality of bytes of data in a consecutively addressed order from an address of a starting byte;
c) a first buffer configured to store a first of the plurality of data lines from the memory array, wherein the first data line comprises the starting byte;
d) a second buffer configured to store a second of the plurality of data lines from the memory array, wherein the second data line is consecutively addressed with respect to the first data line;
e) output circuitry configured to access data from the first buffer, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line;
f) the output circuitry being configured to access data from the second buffer, and to sequentially output each byte from a lowest addressed byte of the second data line until the requested plurality of bytes of data has been output in order to execute the read command; and
g) a data strobe driver configured to clock each byte of data output from the memory device by a data strobe on the interface, wherein the data strobe is activated at a reduced read latency when the starting address is aligned with a lowest addressed byte of the first data line.
2. The memory device of claim 1 , wherein the predetermined number of bytes of data in each data line is 16 bytes.
3. The memory device of claim 1 , further comprising a plurality of sense amplifiers activated to read the predetermined number of bytes of data.
4. The memory device of claim 1 , wherein:
a) the memory array comprises non-volatile memory; and
b) the interface comprises a serial interface.
5. The memory device of claim 1 , wherein the interface is configured to output a byte of data for each transition of the data strobe.
6. The memory device of claim 1 , wherein the data strobe is activated at a standard read latency when the starting address is not aligned with the lowest addressed byte of the first data line.