IP Library Granted Patent US 9,941,148
Granted Patent B2
US 9,941,148 · App. 15/062,168 · Granted Apr 10, 2018

Wafer pin chuck fabrication and repair

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Quick Facts
Patent No.
US 9,941,148
App. No.
15/062,168
Granted
Apr 10, 2018
Kind
B2
Abstract

In a wafer chuck design featuring pins or “mesas” making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits, minimizes sticking of the wafer, and improves wafer settling. In another aspect of the invention is a tool and method for imparting or restoring flatness and roughness to a surface, such as the support surface of a wafer chuck. The tool is shaped such that the contact to the surface being treated is a circle or annulus. The treatment method may take place in a dedicated apparatus, or in-situ in semiconductor fabrication apparatus. The tool is smaller than the diameter of the wafer pin chuck, and may be approximate to the spatial frequency of the high spots to be lapped. The movement of the tool relative to the support surface is such that all areas of the support surface may be processed by the tool, or only those areas needing correction.

Claims (7)

1. A method for lapping a wafer chuck having a wafer support surface that is populated with pins, each of the pins having a pitted terminal surface having a roughness, the terminal surfaces collectively configured to contact and support a semiconductor wafer, said method comprising:

(a) providing a lapping tool having a toroidal surface having a recessed central region (i) having a diameter that is less than that of said wafer chuck;

(b) bringing said lapping tool into contact with said terminal surfaces of said pins of said wafer chuck;

(c) passing said lapping tool over all of said support surface of said wafer chuck, and thereby abrading high spots on said collection of terminal surfaces of said pins, and thereby bringing said collection of terminal surfaces of pins to a flat condition while maintaining a roughness; wherein the toroidal surface and the recessed central region of the tool allows gradual transition as the tool passes over the high spots by maintaining contact with adjacent lower spots of the pins during lapping.

2. The method of claim 1 , wherein the tool is ceramic.

3. The method of claim 1 , wherein the tool is the same material as the pin chuck.

4. The method of claim 1 , wherein said terminal surface has a SPQ plateau roughness of at least 23.9 nm.

Assignments (4)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2020
From: M CUBED TECHNOLOGIES, INC.
To: II-VI DELAWARE, INC.
Reel/Frame 052211/0105 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →