Methods for core recovery after a cold start

1. An apparatus, comprising:

a memory;

a control circuit configured to:

store a plurality of entries, wherein each entry is indicative of a history of at least one branch prediction; and

store a first number of entries in the memory in response to a determination that a first branch instruction is executed after a reset and prior to a first end condition, wherein the first end condition is based on an amount of unused storage in the memory; and

store a second number of entries in the memory in response to a determination that a second branch instruction is executed after the first end condition, wherein the second number is less than the first number.

2. The apparatus of claim 1 , further comprising a cache memory, and wherein the control circuit is further configured to:

pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after the reset and prior to a second end condition, wherein the second end condition is based on an amount of unused storage in the memory; and

pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the second end condition, wherein the second quantity is less than the first quantity.

3. The apparatus of claim 1 , wherein the first end condition is based on a number of entries unsuccessfully allocated after the reset.

4. The apparatus of claim 3 , wherein to allocate the first number of entries, the control circuit is further configured to:

decrement a count value in response to a determination that a given entry of the first number of entries is successfully allocated; and

increment the count value in response to a determination that the given entry of the first number of entries is not successfully allocated.

5. The apparatus of claim 2 , wherein the second end condition is based on a number of cache evictions that occur after the reset.

6. The apparatus of claim 5 , wherein to pre-fetch and store the first quantity of instruction data, the control circuit is further configured to:

decrement a count value in response to a determination that a portion of the first quantity of instruction data was successfully stored in the memory; and

increment the count value in response to a determination that storing the portion of the first quantity of instruction data resulted in an eviction in the memory.

7. The apparatus of claim 1 , wherein the reset corresponds to a power-on reset.

8. A method, comprising:

allocating, by control circuitry, a respective entry into each of a first number of branch history tables stored in a memory in response to determining that a first branch instruction is executed after a reset and prior to a first end condition, wherein the first end condition is based on an amount of unused storage in the memory; and

allocating, by the control circuitry, a respective entry into each of a second number of branch history tables stored in the memory in response to determining that a second branch instruction is executed after the first end condition, wherein the second number is less than the first number.

9. The method of claim 8 , further comprising:

pre-fetching and storing, into a cache memory, a first quantity of instruction data in response to determining that a first pre-fetch operation request is received after the reset and prior to a second end condition, wherein the second end condition is based on an amount of unused storage in the cache memory; and

pre-fetching and storing, into the cache memory, a second quantity of instruction data in response to determining that a second pre-fetch operation request is received after the second end condition, wherein the second quantity is less than the first quantity.

10. The method of claim 9 , wherein prefetching and storing the first quantity of instruction data into the memory includes:

decrementing a count value in response to determining that a given portion of the first quantity of instruction data was successfully stored in a respective location of the memory; and

incrementing the count value in response to determining that storing the given portion of the first quantity of instruction data resulted in an eviction of previously stored instruction data.

11. The method of claim 9 , wherein the second end condition is dependent upon a number of cache evictions that occur after the reset.

12. The method of claim 8 , wherein the first end condition is based on a number of entries unsuccessfully allocated after the reset.

13. The method of claim 8 , wherein allocating the respective entry into each of the first number of branch history tables includes:

decrementing a count value in response to determining that allocating a given entry into one of the first number of branch history tables is successful; and

incrementing the count value in response to determining that allocating the given entry into the one of the first number of branch history tables is unsuccessful.

14. The method of claim 8 , wherein the reset corresponds to a recovery from a reduced power mode.

15. A system, comprising:

a plurality of memories, wherein each memory of the plurality of memories includes a plurality of entries, and wherein each entry of the plurality of entries is configured to store a history of a branch prediction; and

control logic configured to:

allocate a first number of entries of the plurality of entries in respective memories of the plurality of memories in response to a determination that a first branch instruction is executed after a reset and prior to a first end condition, wherein the first end condition is dependent upon a number of unused entries allocated in the memory; and

allocate a second number of entries of the plurality of entries in respective memories of the plurality of memories in response to a determination that a second branch instruction is executed after the first end condition, wherein the second number is less than the first number.

16. The system of claim 15 , wherein the first end condition is dependent upon a number of entries unsuccessfully allocated after the reset, and wherein to allocate the first number of entries, the control logic is further configured to:

decrement a first count value in response to a determination that a given entry of the first number of entries was allocated successfully; and

increment the first count value in response to a determination that the given entry of the first number of entries was not allocated successfully.

17. The system of claim 15 , further comprising a cache memory, wherein the control logic is further configured to:

pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after the reset and prior to a second end condition, wherein the second end condition is dependent upon an amount of unused storage in the cache memory; and

pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the second end condition, wherein the second quantity is less than the first quantity.

18. The system of claim 17 , wherein the second end condition is dependent upon a number of cache evictions that occur after the reset.

19. The system of claim 18 , wherein to pre-fetch and store the first quantity of instruction data, the control logic is further configured to:

decrement a second count value in response to a determination that a given portion of the first quantity of instruction data was successfully stored in the cache memory; and

increment the second count value in response to a determination that storing the given portion of the first quantity of instruction data resulted in a cache eviction.

20. The system of claim 15 , wherein the reset corresponds to an exception generated by a system protection mechanism.