Low capacitance through substrate via structures
View Patent ↗Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.
1. An apparatus, comprising:
a through substrate via formed in an opening formed through a substrate, wherein the opening has at least one sidewall and comprises:
a first dielectric abutted against the at least one sidewall of the opening, the first dielectric including an exposed sidewall on which a barrier layer of tantalum is formed prior to formation of a seed layer of copper on the barrier layer, the first dielectric having a thickness from 1500 to 6000 angstroms thereby covering a sidewall of the opening of the through substrate via including striations and etch features of the at least one sidewall of the opening, the first dielectric disposed such that a top surface of the first dielectric is laterally flush with a top surface of the substrate,
a first conductor abutted against the seed layer, the first conductor having a thickness of around 20 nanometers,
a second dielectric at least formed on the first conductor, and
a second conductor abutted against a sidewall of the second dielectric, the second conductor electroplated on a copper seed layer deposited on a tantalum barrier layer that is previously deposited on the second dielectric, the second conductor formed by filling a remaining portion of the opening formed through the substrate with copper,
wherein the second dielectric is a xerogel or aerogel formed using a deposition process with a thickness of around 3500 angstroms resulting in a capacitance of the through substrate via that is lower than a capacitance value,
wherein a second capacitor formed from the first and second conductors and the second dielectric such that a series combination of capacitances of both of a first capacitor formed by a combination of the substrate, the first dielectric, and the first conductor and the second capacitor is less than or equal to the capacitance of each of the first capacitor and the second capacitor, and
wherein, due to the first dielectric having the thickness from 1500 to 6000 angstroms thereby covering the striations and etch features of the sidewall that otherwise result in formation of cracks in the first dielectric, and further due the first conductor having the thickness of around 20 nanometers, and further due to the second dielectric having the thickness of around 3500 angstroms, the capacitance of the through substrate via is maintained lower than the capacitance value, notwithstanding an increase in a capacitance level of the first capacitor with voltage or time after fabrication.
2. The apparatus of claim 1 , wherein a conductive coupling couples the first conductor to a voltage reference node.
3. The apparatus of claim 2 , wherein the voltage reference node is a ground node.
4. The apparatus of claim 2 , wherein the voltage reference node is a substrate voltage node.
5. The apparatus of claim 1 , wherein the first dielectric is silicon dioxide.
6. The apparatus of claim 1 , further comprising a conductive coupling formed on a top surface of the first conductor, the top surface of the first dielectric, and the top surface of the substrate, wherein portions of a lower surface of the conductive coupling abutting the top surfaces of the first conductor, the first dielectric, and the substrate are co-planar, and wherein a side surface of the conductive coupling and a side surface of the first conductor are co-planar.