IP Library Granted Patent US 9,698,236
Granted Patent B2
US 9,698,236 · App. 15/063,642 · Granted Jul 4, 2017

Semiconductor device and method for manufacturing the same

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Quick Facts
Patent No.
US 9,698,236
App. No.
15/063,642
Granted
Jul 4, 2017
Kind
B2
Abstract

It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Claims (59)

1. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film formed on the substrate; and

a gate electrode formed on the gate insulating film;

wherein the gate insulating film includes silicon, oxygen and nitrogen, a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode and the nitrogen distribution has a first peak and a second peak lower than the first peak, the first peak is located closer to the substrate than the second peak, the first peak has a substrate-side tail included in the gate insulating film.

2. The device according to claim 1 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the first peak.

3. The device according to claim 1 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the second peak.

4. The device according to claim 1 , wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

5. The device according to claim 3 , wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

6. The device according to claim 1 , wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

7. The device according to claim 6 , wherein the continuous region has a physical film thickness of 1 nm or more.

8. The device according to claim 6 , wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

9. The device according to claim 6 , wherein the first peak is located in the continuous region, and the second peak is located out of the continuous region.

10. The device according to claim 1 , wherein a first distance of the first peak from an interface between the substrate and the gate insulating film is longer than a second distance of the second peak from an interface between the gate insulating film and the gate electrode.

11. The device according to claim 1 , wherein the second peak has a gate electrode-sided tail, and the substrate-side tail is steeper than the gate electrode-sided tail of the second peak.

12. The device according to claim 1 , wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

13. The device according to claim 1 , wherein the gate electrode includes polysilicon.

14. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film formed on the substrate; and

a gate electrode formed on the gate insulating film;

wherein the gate insulating film has a multi layered structure and includes silicon, oxygen and nitrogen, a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode, the nitrogen distribution has a first peak and a second peak lower than the first peak, the first peak is located closer to the substrate than the second peak, and the first peak has a substrate-side tail included in the gate insulating film.

15. The device according to claim 14 , wherein the multi layered structure includes three stacked layers with a silicon oxide layer, a silicon oxynitride layer, and a silicon oxide layer.

16. The device according to claim 15 , wherein nitrogen concentration in the silicon oxide layer adjacent to the substrate is 10 atomic % or less.

17. The device according to claim 14 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the first peak.

18. The device according to claim 14 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the second peak.

19. The device according to claim 14 , wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

20. The device according to claim 18 , wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

21. The device according to claim 14 , wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

22. The device according to claim 21 , wherein the continuous region has a physical film thickness of 1 nm or more.

23. The device according to claim 21 , wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

24. The device according to claim 21 , wherein the first peak is located in the continuous region, and the second peak is located out of the continuous region.

25. The device according to claim 14 , wherein a first distance of the first peak from an interface between the substrate and the gate insulating film is longer than a second distance of the second peak from an interface between the gate insulating film and the gate electrode.

26. The device according to claim 14 , wherein the second peak has a gate electrode-sided tail, and the substrate-side tail is steeper than the gate electrode-sided tail of the second peak.

27. The device according to claim 14 , wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

28. The device according to claim 14 , wherein the gate electrode includes polysilicon.

29. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating film including silicon, oxygen, and nitrogen, formed on the substrate; and

a gate electrode formed on the gate insulating film;

wherein a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode,

a region in the gate insulating film where the nitrogen distribution is continuously formed has a first region having a first nitrogen concentration, a second region having a second nitrogen concentration lower than the first nitrogen concentration, and a third region having a third nitrogen concentration lower than the second nitrogen concentration,

the first region is located closer to the substrate than the second and the third region and the third region is located closer to the substrate than the second region, and

a peak of the nitrogen distribution in the first region has a substrate-side tail included in the gate insulating film.

30. The device according to claim 29 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than the first nitrogen concentration.

31. The device according to claim 29 , wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than the second nitrogen concentration.

32. The device according to claim 29 , wherein the first nitrogen concentration is in range of 20 atomic % to 47 atomic %.

33. The device according to claim 31 , wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

34. The device according to claim 29 , wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

35. The device according to claim 34 , wherein the continuous region has a physical film thickness of 1 nm or more.

36. The device according to claim 34 , wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

37. The device according to claim 34 , wherein the first region is located in the continuous region, and the second region is located out of the continuous region.

38. The device according to claim 29 , wherein a peak of the nitrogen distribution in the second region has a gate electrode-side tail, and the substrate-side tail is steeper than the gate electrode-side tail.

39. The device according to claim 29 , wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

40. The device according to claim 29 , wherein the gate electrode includes polysilicon.

41. The device according to claim 1 , wherein the gate insulating film includes Hf.

42. The device according to claim 2 , wherein the gate insulating film includes Hf.

43. The device according to claim 29 , wherein the gate insulating film includes Hf.

44. The device according to claim 30 , wherein the gate insulating film includes Hf.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 043027 FRAME 0072. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043027/0072 →