Resistive random access memory and method for manufacturing the same
A resistive random access memory (RRAM) including a substrate, a dielectric layer, memory cells and an interconnect structure is provided. The dielectric layer is disposed on the substrate. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first electrode, a second electrode and a variable resistance structure. The second electrode is disposed on the first electrode. The variable resistance structure is disposed between the first electrode and the second electrode. In two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other. The interconnect structure is disposed in the dielectric layer and connects the first electrodes of the memory cells.
1. A method of manufacturing a resistive random access memory, comprising:
forming a dielectric layer on a substrate;
forming a plurality of memory cells vertically and adjacently disposed in the dielectric layer, wherein each of the memory cells comprises:
a first electrode;
a second electrode, disposed on the first electrode; and
a variable resistance structure, disposed between the first electrode and the second electrode, wherein
in two vertically adjacent memory cells, the first electrode of the upper memory cell and the second electrode of the lower memory cell are disposed between the adjacent variable resistance structures and isolated from each other, and a method of forming the first electrodes comprises performing a damascene process; and
forming an interconnect structure in the dielectric layer, wherein the interconnect structure connects the first electrodes of the memory cells.
2. The method of manufacturing the resistive random access memory according to claim 1 , wherein a method of forming the dielectric layer comprises performing a chemical vapor deposition process.
3. The method of manufacturing the resistive random access memory according to claim 1 , wherein a method of forming each of the variable resistance structures and each of the second electrodes comprises:
forming an opening in the dielectric layer;
forming a conformal variable resistance material layer in the opening;
forming a conductive material layer filling up the opening; and
removing the conductive material layer and the variable resistance material layer outside the opening.
4. The method of manufacturing the resistive random access memory according to claim 3 , wherein a method of forming the opening comprises performing a patterning process on the dielectric layer.
5. The method of manufacturing the resistive random access memory according to claim 3 , wherein a method of forming the variable resistance material layer comprises performing a chemical vapor deposition process.
6. The method of manufacturing the resistive random access memory according to claim 3 , wherein a method of foaming the conductive material layer comprises performing an electroplating process or a physical vapor deposition process.
7. The method of manufacturing the resistive random access memory according to claim 3 , wherein a method of removing the conductive material layer and the variable resistance material layer outside the opening comprises performing a chemical mechanical polishing process.
8. The method of manufacturing the resistive random access memory according to claim 3 , wherein a method of forming each of the variable resistance structures further comprises forming a conformal insulation material layer before or after forming the variable resistance material layer.
9. The method of manufacturing the resistive random access memory according to claim 8 , wherein a method of forming the insulation material layer comprises performing a chemical vapor deposition process.
10. The method of manufacturing the resistive random access memory according to claim 1 , wherein a method of limning the interconnect structure comprises performing a damascene process.
11. The method of manufacturing the resistive random access memory according to claim 1 , further comprising:
before forming the dielectric layer, forming a transistor on the substrate, wherein a terminal of the transistor is connected with the interconnect structure.