Retention optimized memory device using predictive data inversion

1. A method of providing a dynamic random access memory (DRAM) integrated circuit, comprising:

providing an external signal interface, comprising:

a plurality of interface circuits, wherein:

each interface circuit is adapted to be coupled to an external signal line for the input and output of binary external data, wherein a first voltage range on the external signal line corresponds to a first binary logic state and a second voltage range on the external signal line corresponds to a second binary logic state, and

the logic polarity of the external data is statistically distributed to favor the first binary logic state;

providing a memory array, comprising:

a plurality of memory cells, wherein:

each memory cell comprises a data storage capacitor, wherein charging the capacitor to a third voltage range corresponds to a third binary logic state and charging the capacitor to a fourth voltage range corresponds to a fourth binary logic state,

a leakage current in each memory cell is substantially larger when its capacitor charged to the third voltage range, and

the leakage current in each memory cell is substantially smaller when its capacitor charged to the fourth voltage range; and

providing a plurality of selective inversion circuits coupled between the plurality of interface circuits and the memory array and adapted to minimize the leakage current of the memory array, wherein:

external data is stored in the array such that data in the first binary logic state is stored in each memory cell as the fourth binary logic state and the second binary logic state is stored in a memory cell as the third binary logic state.

2. The method of providing a DRAM integrated circuit of claim 1 , further comprising:

providing a plurality of sense amplifier circuits coupled between the plurality of selective inversion circuits and the memory array; and

providing a plurality of output selective inversion circuits coupled to the plurality of sense amplifier circuits, wherein:

the selective inversion circuits provide external data in differential format to the sense amplifier circuits during a write memory access, and

the sense amplifier circuits provide stored data in differential format to the output selective inversion circuits during a read memory access.

3. The method of providing a DRAM integrated circuit of claim 2 , further comprising:

providing an address path coupled to the memory array, the plurality of selective inversion circuits, and the plurality of output selective inversion circuits, wherein:

the address path selects a portion of the plurality of memory cells for a memory access,

the selective inversion of the external data is determined by the address path, and

the selective inversion is the same for both read memory accesses and write memory accesses to the same selected portion of the plurality of memory cells.

4. The method of providing a DRAM integrated circuit of claim 3 , wherein:

the first and second binary states correspond to a single high-low pair representing a binary bit on an external signal line; and

the third and fourth binary states correspond to a single high-low pair representing a single binary bit stored in a memory cell.

5. The method of providing a DRAM integrated circuit of claim 4 , wherein:

the first binary logic state corresponds to a logic high state and the second binary state corresponds to a logic low state.

6. The method of providing a DRAM integrated circuit of claim 4 , wherein:

the third binary logic state corresponds to a logic high state and the fourth binary state corresponds to a logic low state.

7. A method of providing a dynamic random access memory (DRAM) integrated circuit, comprising:

providing an external signal interface, comprising:

a plurality of interface circuits, wherein:

each interface circuit is adapted to be coupled to an external signal for the input and output of external binary data, wherein a first voltage range corresponds to a first binary logic state and a second voltage range corresponds to a second binary logic state, and

the logic polarity of the external binary data is distributed to favor statistically the first binary logic state;

providing a memory array, comprising:

a plurality of memory cells organized into rows and columns, wherein:

each memory cell comprises a data storage capacitor, wherein charging the capacitor to a third voltage range corresponds to a third binary logic state and charging the capacitor to a fourth voltage range corresponds to a fourth binary logic state,

a leakage current in each memory cell is substantially larger when its capacitor charged to the third voltage range, and

the leakage current in each memory cell is substantially smaller when its capacitor charged to the fourth voltage range,

a plurality of positive and negative bit line pairs each associated with one column, wherein:

each memory cell is coupled to only one bit line,

an equal number of memory cells are coupled to each bit line, and

the positive and negative bit lines in a bit line pair are adapted to transmit data to and from the memory cells differentially in positive and negative binary logic polarity respectively, and

a plurality of positive and negative word lines running parallel to the rows of memory cells, wherein:

each memory cell is coupled to only one word line,

positive word lines are coupled to memory cells which are coupled to positive bit lines, and

negative word lines are coupled to memory cells which are coupled to negative bit lines;

providing a plurality of sense amplifiers coupled between the plurality of interface circuits and the array of memory cells, wherein:

each sense amplifier is associated with one column, and

each sense amplifier comprises a positive node coupled to the associated positive bit line and a negative node coupled to the associated negative bit line; and

providing a control circuit, comprising:

an address decoder circuit coupled to the plurality of word lines, and

a plurality of selective inversion circuits coupled to the address decoder and further coupled between the plurality of interface circuits and the plurality of sense amplifiers and adapted to minimize the leakage current of the memory array, wherein:

the address decoder selects a word line for a write memory access,

if the selected word line is a positive word line, then the external binary data is inverted by the selective inversion circuits and stored in the array such that the first binary logic state is stored in each accessed memory cell as the fourth binary logic state and the second binary logic state is stored in each accessed memory cell as the third binary logic state, and

if the selected word line is a negative word line, then the external binary data is not inverted by the selective inversion circuits and stored in the array such that the first binary logic state is stored in each accessed memory cell as the fourth binary logic state and the second binary logic state is stored in each accessed memory cell as the third binary logic state.

8. The method of providing a DRAM integrated circuit of claim 7 , wherein:

the first and second binary states correspond to a single high-low pair representing a binary bit on an external signal line; and

the third and fourth binary states correspond to a single high-low pair representing a single binary bit stored in a memory cell.

9. The method of providing a DRAM integrated circuit of claim 8 , wherein:

the first binary logic state corresponds to a logic high state and the second binary state corresponds to a logic low state.

10. The method of providing a DRAM integrated circuit of claim 8 , wherein:

the third binary logic state corresponds to a logic high state and the fourth binary state corresponds to a logic low state.