IP Library › Granted Patent US 9,941,016
Granted Patent B2
US 9,941,016 · App. 15/065,920 · Granted Apr 10, 2018

Flash memory device performing adaptive loop, memory system and method of operating the memory system

Inventors: Young-Seop Shim (Seoul, KR); Jae-Hong Kim (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
G11C16/3495G11C7/04G11C16/10G11C16/16G11C16/349G11C16/3445G11C16/3459G11C11/5628G11C11/5635
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,941,016
App. No.
15/065,920
Granted
Apr 10, 2018
Kind
B2
Abstract

A method of operating a flash memory device includes detecting the number of program/erase cycles that have been executed by the flash memory device. A setting value related to the number of times a program loop is performed is changed according to the detected number of program/erase cycles. Data is programmed within the flash memory by performing the program loop one or more times, in response to receiving a write command. A determination is made whether the programming has passed or failed, based on whether the number of program loops required to program the data within the flash memory is within a boundary identified by the changed setting-value.

Claims (47)

1. A method of operating a flash memory device, the method comprising:

detecting a number of program/erase cycles that have been executed by the flash memory device;

changing, in accordance with the detected number of program/erase cycles, a maximum value of a number of times a program loop is executed, wherein the maximum value of the number of times the program loop is executed decreases as the number of executed program/erase cycles increases;

programming data within the flash memory device by executing the program loop one or more times, in response to receiving a write command; and

determining whether the programming has passed or failed, based on whether a number of program loops required to program the data within the flash memory device is within a range bounded by the changed maximum value.

2. The method of claim 1 , wherein the programming passes when the programming of the data within the flash memory device is completed with an executed number of program loops that is within the range bounded by the changed maximum value.

3. The method of claim 1 , wherein a block comprising a write-requested page is processed as a bad block when the programming is determined to have failed for the write-requested page.

4. The method of claim 1 , wherein the detecting of the number of program/erase cycles comprises:

generating a count value by performing a count operation in response to a reception of a write/erase command; and

determining a timing for changing the maximum value, by comparing the count value with a reference value.

5. The method of claim 1 , wherein the changing of the maximum value comprises referring to a look-up table comprising table information related to a result of the detecting and the number of times the program loop is performed.

6. The method of claim 1 , further comprising:

changing, in accordance with the detected number of program/erase cycles, a maximum erase value of a number of times an erase loop is executed;

erasing data within the flash memory device by executing the erase loop one or more times, in response to receiving an erase command; and

determining whether the erasing has passed or failed, based on whether a number of erase loops required to erase the data within the flash memory device is within a range bounded by the changed maximum erase value.

7. The method of claim 6 , wherein an erase-requested block is processed as a bad block when the erasing is determined to have failed for the erase-requested block.

8. The method of claim 1 , wherein:

the flash memory device comprises a plurality of memory chips and each of the memory chips comprises a plurality of cell regions, and

the maximum value is set differently for each memory chip or is set differently for each cell region.

9. The method of claim 1 , wherein the changing of the maximum value is further based on at least one selected from:

a detected temperature of the flash memory device; and

at least one of a detected voltage and a detected current that is transmitted to a word line of the flash memory device.

10. A method of operating a memory system comprising a memory controller and a memory device, the method comprising:

performing a first memory operation including program loops or erase loops to program or erase data;

detecting a number of program/erase cycles that have been executed by the memory device;

changing a maximum number of loops of a program operation or an erase operation into N, according to the detected number of program/erase cycles (N is an integer of 1 or greater);

performing a second memory operation including program loops or erase loops to program or erase data without exceeding the changed maximum number of loops;

determining whether the second memory operation has passed or failed, based on the changed, maximum number of loops; and

managing a cell region, for which the second memory operation is requested, as a bad region if the second memory operation is determined to have failed, wherein:

when it is determined that the first memory operation has failed after an Nth program loop or erase loop is performed, an (N+1)th program loop or erase loop is further performed, and

when it is determined that the second memory operation has failed after an Nth program loop or erase loop is performed, the cell region is managed as the bad region.

11. The method of claim 10 , wherein as the number of program/erase cycles increases, the maximum number of loops of the program operation gradually decreases and the maximum number of loops of the erase operation gradually increases.

12. The method of claim 10 , wherein:

the second memory operation comprises a program operation corresponding to a write command and an erase operation corresponding to an erase command, and

a block comprising a program-failed page and an erase-failed block are managed as bad blocks.

13. The method of claim 10 , wherein:

the detected number of program/erase cycles is provided to the memory controller, and

in an initial driving of the memory system, the memory controller refers to a look-up table comprising information related to the detected number of program/erase cycles and a number of times a program loop is performed and communicates a setting of the maximum number of loops to the memory device.

14. A method executed by a nonvolatile memory device of programming or erasing data within the nonvolatile memory device, the method comprising:

selecting an upper boundary of program or erase loops that varies in accordance with a parameter of the nonvolatile memory device;

executing operational loops for programming or erasing data within the nonvolatile memory device; and

determining whether the data is successfully programmed or erased within the nonvolatile memory device through a number of the executed operational loops that is within the selected upper boundary, wherein

for a circumstance in which the operational loops are executed for programming data within the nonvolatile memory device, the upper boundary decreases as a number of executed program and erase cycles increases.

15. The method of claim 14 , wherein the parameter is a number of executed program and erase cycles that have been executed by the nonvolatile memory device.

16. The method of claim 14 , wherein the parameter is a time required for the nonvolatile memory device to perform an operation or a temperature of the nonvolatile memory device.

17. The method of claim 15 , wherein for a circumstance in which the operational loops are executed for erasing data within the nonvolatile memory device, the upper boundary increases as a number of executed program and erase cycles increases.

18. The method of claim 14 , wherein the parameter is a detected current that is transmitted to a word line of the nonvolatile memory device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2016
From: SHIM, YOUNG-SEOP; KIM, JAE-HONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 038039/0867 →
Priority Claims (1)
KR 10-2015-0088722 · Jun 22, 2015 · national
Continuity (1)
Related Publication 20160371026A1 · Dec 22, 2016