Conductive hard mask for memory device formation
View Patent ↗Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.
1. A method of forming a memory cell array, comprising:
forming a memory element layer that comprises a variable resistance material;
forming a conductive layer on the memory element layer;
forming a conductive hard mask on the conductive layer;
forming an insulative hard mask on the conductive hard mask; and
forming a sealant on the insulative hard mask, the insulative hard mask formed of a different material than the conductive hard mask and the sealant.
2. The method of claim 1 , further comprising:
forming a pattern in the conductive hard mask and the additional insulative hard mask.
3. The method of claim 1 , further comprising:
forming a pattern in the conductive hard mask.
4. The method of claim 3 , wherein forming the pattern in the conductive hard mask comprises:
forming the pattern using photolithography and etching.
5. The method of claim 3 , further comprising:
removing a first portion of the conductive layer and a first portion of the memory element layer; and
retaining a second portion of the conductive layer and a second portion the memory element layer under the pattern of the conductive hard mask.
6. The method of claim 5 , further comprising:
removing a portion of the patterned conductive hard mask.
7. The method of claim 6 , wherein removing the portion of the patterned conductive hard mask comprises:
removing the patterned conductive hard mask using a chemical-mechanical planarization (CMP) process.
8. The method of claim 7 , wherein removing the portion of the patterned conductive hard mask comprises:
exposing at least some of the second portion of the conductive layer.
9. The method of claim 8 , further comprising:
forming a conductive line on the second portion of the conductive layer.
10. The method of claim 6 , wherein removing the portion of the patterned conductive hard mask comprises:
retaining a portion of the conductive hard mask.
11. The method of claim 10 , further comprising:
forming a conductive line on the retained portion of the conductive hard mask.
12. The method of claim 1 , wherein the conductive layer comprises carbon, tungsten, aluminum, titanium, titanium nitride, silicon, or any combination thereof.
13. The method of claim 1 , wherein the conductive hard mask comprises at least one of tungsten, aluminum, titanium, titanium nitride, silicon, or any combination thereof, and wherein the conductive hard mask and the conductive layer comprise different materials.
14. A method of forming a memory cell, comprising:
forming a memory element layer that comprises a variable resistance material;
forming a conductive layer on the memory element layer;
forming a conductive hard mask on the conductive layer;
forming an insulative hard mask on the conductive hard mask;
forming a sealant on a top surface and a sidewall of a stack that includes the memory element layer, the conductive layer, the conductive hard mask, and the insulative hard mask, the insulative hard mask formed of a different material than the conductive hard mask and the sealant; and
removing the insulative hard mask using a chemical-mechanical planarization (CMP) process based at least in part on forming the sealant.
15. The method of claim 14 , further comprising:
forming a pattern in the conductive hard mask and the insulative hard mask; and
etching the memory element layer and the conductive layer according to the pattern, wherein the etching retains a portion of the conductive layer and a portion of the memory element layer under the conductive hard mask and the insulative hard mask.
16. The method of claim 1 , further comprising:
forming a stack having a sidewall by removing a first portion of the conductive layer and a first portion of the memory element layer not under the conductive hard mask and the insulative hard mask, wherein forming the sealant is based at least in part on forming the stack.
17. The method of claim 1 , further comprising:
removing a first portion of the sealant to expose a top surface of the insulative hard mask.
18. The method of claim 17 , further comprising:
forming an interconnect by depositing a material on the top surface of the insulative hard mask based at least in part on removing the first portion of the sealant.
19. The method of claim 17 , further comprising:
removing the insulative hard mask to expose a top surface of the conductive hard mask based at least in part on removing the first portion of the sealant.
20. The method of claim 19 , further comprising:
forming a bit line that contacts the top surface of the conductive hard mask after removing the insulative hard mask.
21. The method of claim 19 , further comprising:
removing a first portion of a material that forms an interconnect to expose the top surface of the insulative hard mask, wherein removing the insulative hard mask is based at least in part on removing the first portion of the material.