Semiconductor device and manufacturing method thereof

1. A semiconductor device comprising:

a substrate comprising a surface;

a graphene layer provided on the surface of the substrate, the graphene layer containing impurities, and including a first region and a second region, the first region being adjacent to the second region, the first region and the second region not overlapping when viewed from above the surface of the substrate, the second region having a resistance higher than a resistance of the first region, and the second region including a side surface of the graphene layer;

a first plug being in contact with the first region;

a first film covering the graphene layer but exposing said side surface of the graphene layer; and

a second film covering said side surface of the graphene layer,

wherein a concentration of the impurities in the first region is greater than or equal to a certain value, and the second region includes a region in which a concentration of the impurities is lower than the certain value, and

wherein the concentration of the impurities in the second region increases in a direction from said side surface of the graphene layer toward the first region.

2. The device of claim 1 , wherein the first film contains a nitride, and the second film contains one of an oxide and a nitride.

3. The device of claim 1 , further comprising a second plug which is in contact with the graphene layer, wherein one of the first plug and the second plug is in contact with a lower surface of the first region, and the other one of the first plug and the second plug is in contact with an upper surface of the first region.

4. The device of claim 3 , wherein the first plug and the second plug are in contact with the first region without being in contact with the second region.

5. The device of claim 1 , wherein the second region has a length of 10 μm or greater.

6. The device of claim 1 , wherein the first region is longer than the second region.

7. The device of claim 1 , wherein the graphene layer further includes a third region, and the third region has a resistance higher than the resistance of the first region and includes a side surface of the other end of the graphene layer.

8. The device of claim 7 , wherein a concentration of the impurities in the third region is lower than the concentration of the impurities in the first region.

9. The device of claim 1 , wherein the graphene layer constitutes an interconnect.

10. The device of claim 1 , further comprising another graphene layer which includes two regions corresponding to the first and second regions of the graphene layer respectively, wherein the two regions of the another graphene layer are different in resistances.

11. The device of claim 1 , wherein the impurities include at least one of Li, Na, K, Cs, Ca, Sr, Ba, Sm, Eu, Yb, Tm, F 2 , Br 2 , ICl, IBr, MgCl 2 , AlCl 3 , FeCl 3 , CuCl 2 , SbCl 5 , MoCl 5 , AsF 5 , SbF 5 , NbF 5 , HNO 5 , H 2 SO 4 , H 3 PO 4 and HF.

12. The device of claim 1 , wherein the first film comprises an upper portion covering an upper surface of the first region, and a side portion covering another side surface of the graphene layer.

13. The device of claim 12 , wherein the second film further covers the upper portion and the side portion of the first film.

14. The device of claim 13 , wherein the first plug penetrates the first film and the second film to be in contact with the upper surface of the first region.