Semiconductor device and method for fabricating the same
View Patent ↗Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
1. A semiconductor device comprising:
a substrate on which a first region and a second region are defined;
first and second gate structures arranged on the first and second regions, respectively; and
a capping layer covering the first and second gate structures,
wherein the first gate structure includes a first interface layer arranged on the substrate, a first high-k dielectric layer arranged on the first interface layer, a first diffusion layer arranged on the first high-k dielectric layer, a first barrier layer arranged on the first diffusion layer, a first work function adjustment layer arranged on the first barrier layer, a third barrier layer arranged on the first work function adjustment layer, and a gate metal arranged on the first work function adjustment layer, and
wherein the second gate structure includes a second interface layer arranged on the substrate, a second high-k dielectric layer arranged on the second interface layer, a second diffusion layer arranged on the second high-k dielectric layer, a second barrier layer arranged on the second diffusion layer, a second work function adjustment layer arranged on the second barrier layer, a third work function adjustment layer arranged on the second work function adjustment layer, and a fourth barrier layer arranged on the third work function adjustment layer.
2. The semiconductor device of claim 1 , further comprising:
a first fin projecting from the first region and extending in a first direction; and
a second fin projecting from the second region and extending in the first direction,
wherein the first gate structure is arranged on the first fin to cross the first fin, and the second gate structure is arranged on the second fin to cross the second fin.
3. The semiconductor device of claim 1 , wherein the first work function adjustment layer and the third work function adjustment layer include the same material.
4. The semiconductor device of claim 1 , wherein the number of layers included in the first gate structure is different from the number of layers included in the second gate structure.
5. The semiconductor device of claim 1 , wherein the capping layer includes at least one of SiN, SiON, and SiCON.
6. The semiconductor device of claim 1 , wherein the first region includes an NFET region, and the second region includes a PFET region.
7. The semiconductor device of claim 1 , wherein a thickness of the first barrier layer is 3 to 30 Å.
8. The semiconductor device of claim 1 , wherein the diffusion layer and the first barrier layer comprise different materials.
9. The semiconductor device of claim 8 , wherein the diffusion layer comprises Ti, and the first barrier layer comprises Ta.
10. The semiconductor device of claim 1 , wherein a thickness of the capping layer is 5 to 500 Å.
11. The semiconductor device of claim 10 , wherein the capping layer comprises an oxide layer.
12. The semiconductor device of claim 10 , wherein the capping layer comprises a nitride layer.