Array substrate, driving method thereof and electronic paper

1. An array substrate, comprising:

a base substrate;

a plurality of gate lines and a plurality of data lines disposed on the base substrate, the plurality of gate lines and the plurality of data lines being insulated from each other and extending across each other;

a gate driving circuit integrated on the base substrate and electrically connected with the gate lines and a data driving circuit integrated on the base substrate and electrically connected with the data lines; wherein:

during a display period of a frame, the gate driving circuit is configured to load gate scanning signals to the gate lines sequentially and respectively; and while each gate line is loaded with a respective gate scanning signal, the data driving circuit is configured to transmit data signals to the data lines;

the data driving circuit comprises a plurality of data driving sub-circuits that are in one-to-one correspondence with the data lines, each data driving sub-circuit comprises a control unit, a switch unit and a memory unit; and

in each data driving sub-circuit:

the control unit is configured to control the switch unit in the data driving sub-circuit to be turned on such that the data driving sub-circuit transmits a data signal to a data line corresponding to the data driving sub-circuit; and

the memory unit in the data driving sub-circuit is configured to store the data signal when the switch unit in the data driving sub-circuit is turned on.

2. The array substrate of claim 1 , wherein

the data driving sub-circuits receive data signals via a same signal line, and the data driving sub-circuits are configured to transmit the received data signals to the data lines sequentially.

3. The array substrate of claim 1 , wherein the data driving sub-circuits are divided into at least two groups, and the data driving sub-circuits in each same group receive data signals via a same signal line, and

wherein the two groups of data driving sub-circuits are configured to transmit received data signals to data lines corresponding to the respective groups of data driving sub-circuits simultaneously, and within each group, corresponding data driving sub-circuits in that group are configured to transmit the received data signals to the data lines corresponding to the data driving sub-circuits in that group sequentially.

4. The array substrate of claim 3 , wherein the data driving sub-circuits are divided into two groups, one group comprises data driving sub-circuits corresponding to data lines at odd-numbered columns, and another group comprises data driving sub-circuits corresponding to data lines at even-numbered columns.

5. The array substrate of claim 1 , wherein the control unit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor and a second capacitor;

a gate and a source of the first switching transistor are electrically connected with a signal input terminal, and a drain of the first switching transistor is electrically connected with a first node;

a gate of the second switching transistor is electrically connected with a reset signal terminal, a source of the second switching transistor is configured to receive a signal with a low voltage level, and a drain of the second switching transistor is electrically connected with the first node;

a gate of the third switching transistor is electrically connected with the first node, a source of the third switching transistor is configured to receive a second timing signal, and a drain of the third switching transistor is electrically connected with a signal output terminal;

a gate of the fourth switching transistor is electrically connected with the reset signal terminal, a source of the fourth switching transistor is configured to receive the signal with a low voltage level, and a drain of the fourth switching transistor is electrically connected with the signal output terminal;

a first terminal of the first capacitor is configured to receive a first timing signal, a second terminal of the first capacitor is electrically connected with the first node; and

a first terminal of the second capacitor is electrically connected with the first node, and a second terminal of the second capacitor is electrically connected with the output signal terminal.

6. The array substrate of claim 5 , wherein control units corresponding to the data driving sub-circuits are connected in a concatenation approach;

other than a control unit in a first stage, a signal output terminal of each control unit in any other stage is connected with a reset signal terminal of a previous adjacent control unit;

other than a control unit in a last stage, a signal output terminal of each control unit in any other stage is connected with a signal input terminal of a next adjacent control unit;

a signal input terminal of the control unit in the first stage is configured to receive a start triggering signal; and

a reset signal terminal of the control unit in the last stage is configured to receive a termination reset signal.

7. The array substrate of claim 1 , wherein the switch unit comprises a fifth switching transistor, and

in each data driving sub-circuit:

a gate of the fifth switching transistor in the data driving sub-circuit is electrically connected with a signal output terminal of the control unit in the data driving sub-circuit, a source of the fifth switching transistor is electrically connected with a data signal terminal, and a drain of the fifth switching transistor is electrically connected with a data line corresponding to the data driving sub-circuit.

8. The array substrate of claim 7 , wherein the memory unit comprises a third capacitor; and

in each data driving sub-circuit:

a first terminal of the third capacitor in the data driving sub-circuit is electrically connected with the drain of the fifth switching transistor in the data driving sub-circuit, and a second terminal of the third capacitor is grounded.

9. An electronic paper, comprising the array substrate of claim 1 .

10. A driving method for the array substrate of claim 2 , comprising:

during a display period of a frame, loading the gate scanning signals to the gate lines sequentially by the gate driving circuit; and while each gate line is loaded with a respective gate scanning signal, transmitting the data signals to the data lines sequentially by the data driving sub-circuits.

11. A driving method for the array substrate of claim 3 , comprising:

during a display period of a frame, loading the gate scanning signals to the gate lines sequentially by the gate driving circuit; and

while each gate line is loaded with a respective gate scanning signal, transmitting, by respective groups of data driving sub-circuits, data signals to data lines corresponding to the respective groups of data driving sub-circuits simultaneously, and within each group of data driving sub-circuits, transmitting, by data driving sub-circuits in the group, data signals to data lines corresponding to the data driving sub-circuits in the group sequentially.

12. The method of claim 11 , wherein while each gate line is loaded with a respective gate scanning signal, transmitting, by respective groups of data driving sub-circuits, data signals to data lines corresponding to the respective groups of data driving sub-circuits simultaneously, and within each group of data driving sub-circuits, transmitting, by data driving sub-circuits in the group, data signals to data lines corresponding to the data driving sub-circuits in the group sequentially comprises:

transmitting, by a first group of data driving sub-circuits corresponding to data lines at odd-numbered columns, data signals to the data lines at the odd-numbered columns sequentially; and

at the same time, transmitting, by a second group of data driving sub-circuits corresponding to data lines at even-numbered columns, data signals to the data lines at the even-numbered columns sequentially.

13. The array substrate of claim 1 , wherein the gate driving circuit comprises a plurality of shift registers that are in one-to-one correspondence with the gate lines, and

wherein the shift registers are electrically connected with pins on the array substrate, and the pins are electrically connected with a printed circuit board bonded on the array substrate.

14. The array substrate of claim 13 , wherein the printed circuit board controls the shift registers to load the gate scanning signals to the gate lines sequentially.

15. The array substrate of claim 13 , wherein

the data driving sub-circuits receive the data signals via a same signal line, the same signal line being connected with the pins, and

the printed circuit board controls, through the same signal line, the data driving sub-circuits to load the data signals to the data lines sequentially and respectively.

16. The array substrate of claim 13 , wherein

the data driving sub-circuits are divided into two groups; and

for each group of data driving sub-circuits:

data driving sub-circuits in the group receive data signals via a same signal line, the same signal line being connected with the pins; and

the printed circuit board controls, through the same signal line, the data driving sub-circuits in the group to load the data signals to data lines that corresponds to the data driving sub-circuits in the group sequentially and respectively.

17. An array substrate, comprising:

a base substrate;

a plurality of gate lines and a plurality of data lines disposed on the base substrate, the plurality of gate lines and the plurality of data lines being insulated from each other and extending across each other;

a gate driving circuit disposed on the base substrate and electrically connected with the gate lines; and

a data driving circuit disposed on the base substrate and electrically connected with the data lines; wherein:

during a display period of a frame, the gate driving circuit is configured to load gate scanning signals to the gate lines sequentially and respectively; and while each gate line is loaded with a respective gate scanning signal, the data driving circuit is configured to transmit data signals to the data lines;

the data driving circuit comprises a plurality of data driving sub-circuits that are in one-to-one correspondence with the data lines;

the data driving sub-circuits receive data signals via a same signal line; and the data driving sub-circuits are configured to transmit the received data signals to the data lines sequentially;

each data driving sub-circuit comprises a control unit, a switch unit and a memory unit;

in each data driving sub-circuit:

the control unit is configured to control the switch unit in the data driving sub-circuit to be turned on such that the data driving sub-circuit transmits a data signal to a data line corresponding to the data driving sub-circuit; and

the memory unit in the data driving sub-circuit is configured to store the data signal when the switch unit in the data driving sub-circuit is turned on;

the control unit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor and a second capacitor;

a gate and a source of the first switching transistor are electrically connected with a signal input terminal, and a drain of the first switching transistor is electrically connected with a first node;

a gate of the second switching transistor is electrically connected with a reset signal terminal, a source of the second switching transistor is configured to receive a signal with a low voltage level, and a drain of the second switching transistor is electrically connected with the first node;

a gate of the third switching transistor is electrically connected with the first node, a source of the third switching transistor is configured to receive a second timing signal, and a drain of the third switching transistor is electrically connected with a signal output terminal;

a gate of the fourth switching transistor is electrically connected with the reset signal terminal, a source of the fourth switching transistor is configured to receive the signal with a low voltage level, and a drain of the fourth switching transistor is electrically connected with the signal output terminal;

a first terminal of the first capacitor is configured to receive a first timing signal, a second terminal of the first capacitor is electrically connected with the first node; and

a first terminal of the second capacitor is electrically connected with the first node, and a second terminal of the second capacitor is electrically connected with the output signal terminal.

18. An array substrate, comprising:

a base substrate;

a plurality of gate lines and a plurality of data lines disposed on the base substrate, the plurality of gate lines and the plurality of data lines being insulated from each other and extending across each other;

a gate driving circuit disposed on the base substrate and electrically connected with the gate lines; and

a data driving circuit disposed on the base substrate and electrically connected with the data lines; wherein:

during a display period of a frame, the gate driving circuit is configured to load gate scanning signals to the gate lines sequentially and respectively; and while each gate line is loaded with a respective gate scanning signal, the data driving circuit is configured to transmit data signals to the data lines;

the data driving circuit comprises a plurality of data driving sub-circuits that are in one-to-one correspondence with the data lines;

the data driving sub-circuits are divided into at least two groups; the data driving sub-circuits in each same group receive data signals via a same signal line;

the two groups of data driving sub-circuits are configured to transmit received data signals to data lines corresponding to the respective groups of data driving sub-circuits simultaneously, and within each group, corresponding data driving sub-circuits in that group are configured to transmit the received data signals to the data lines corresponding to the data driving sub-circuits in that group sequentially;

each data driving sub-circuit comprises a control unit, a switch unit and a memory unit;

in each data driving sub-circuit:

the control unit is configured to control the switch unit in the data driving sub-circuit to be turned on such that the data driving sub-circuit transmits a data signal to a data line corresponding to the data driving sub-circuit; and

the memory unit in the data driving sub-circuit is configured to store the data signal when the switch unit in the data driving sub-circuit is turned on;

the control unit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor and a second capacitor;

a gate and a source of the first switching transistor are electrically connected with a signal input terminal, and a drain of the first switching transistor is electrically connected with a first node;

a gate of the second switching transistor is electrically connected with a reset signal terminal, a source of the second switching transistor is configured to receive a signal with a low voltage level, and a drain of the second switching transistor is electrically connected with the first node;

a gate of the third switching transistor is electrically connected with the first node, a source of the third switching transistor is configured to receive a second timing signal, and a drain of the third switching transistor is electrically connected with a signal output terminal;

a gate of the fourth switching transistor is electrically connected with the reset signal terminal, a source of the fourth switching transistor is configured to receive the signal with a low voltage level, and a drain of the fourth switching transistor is electrically connected with the signal output terminal;

a first terminal of the first capacitor is configured to receive a first timing signal, a second terminal of the first capacitor is electrically connected with the first node; and

a first terminal of the second capacitor is electrically connected with the first node, and a second terminal of the second capacitor is electrically connected with the output signal terminal.