Memory system design using buffer(s) on a mother board

1. A system comprising:

a processor coupled to one or more communication channels to communicate commands;

a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board, wherein at least one DIMM in said first set of two or more DIMMs comprises a first internal data buffer coupled to said first primary data buffer via said first communication channel;

a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on said mother board, wherein at least one DIMM in said second set of two or more DIMMs comprises a second internal data buffer coupled to said second primary data buffer via said second communication channel; and

a third communication channel electrically coupling said first primary data buffer to said second primary data buffer, and coupling said first primary data buffer and said second primary data buffer to said processor.

2. The system of claim 1 , wherein said first communication channel is coupled in parallel to DIMMs in said first set of two or more DIMMs.

3. The system of claim 1 , wherein said second communication channel is coupled in parallel to DIMMs in said second set of two or more DIMMs.

4. The system of claim 1 , wherein:

said processor comprises a controller that is programmable; and

said controller is configured to respond to commands to access content stored in one or more of a plurality of memory devices distributed throughout said first and second sets of two or more DIMMs and to perform data operations on content accessed from said plurality of memory devices.

5. The system of claim 4 , wherein said controller comprises a field programmable gate array (FPGA).

6. The system of claim 4 , wherein said plurality of memory devices comprises memory devices packaged in a DIMM comprising at least one of a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), or an unregistered DIMM (UDIMM).

7. The system of claim 1 , wherein said first and second sets of two or more DIMMs comply with a double data-rate (DDR) standard or one of its derivatives.

8. The system of claim 1 , further comprising a plurality of I2C buses, each I2C bus coupling said processor to a corresponding DIMM in said first set of two or more DIMMs or said second set of two or more DIMMs and configured for communicating an alert.

9. The system of claim 1 , further comprising a plurality of I2C buses, each I2C bus coupling said processor to a corresponding DIMM in said first set of two or more DIMMs or said second set of two or more DIMMs and configured for performing calibration.

10. The system of claim 1 , wherein said third communication channel comprises a BCOM bus.

11. A system comprising:

a plurality of memory devices;

a memory controller configured to respond to commands from a command interface to access content stored in one or more of said plurality of memory devices and to perform data operations on content accessed from said plurality of memory devices;

a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) comprising memory devices and a first primary data buffer on a mother board, wherein at least one DIMM in said first set of two or more DIMMs comprises a first internal data buffer coupled to said first primary data buffer via said first communication channel;

a second communication channel electrically coupling a second set of two or more DIMMs comprising memory devices and a second primary data buffer on said mother board, wherein at least one DIMM in said second set of two or more DIMMs comprises a second internal data buffer coupled to said second primary data buffer via said second communication channel; and

a third communication channel electrically coupling said first primary data buffer to said second primary data buffer, and coupling said first primary data buffer and said second primary data buffer to said memory controller.

12. The system of claim 11 , wherein said memory controller is programmable.

13. The system of claim 12 , wherein said memory controller comprises a field programmable gate array (FPGA).

14. The system of claim 11 , wherein said plurality of memory devices comprise memory devices packaged in load reduced DIMM (LRDIMM).

15. The system of claim 11 , wherein said first primary data buffer and said first internal data buffer are identical.

16. The system of claim 11 , wherein said first primary data buffer and said second primary data buffer are configured to sample and retransmit data.

17. A system comprising:

a processor coupled to one or more communication channels to communicate commands;

a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board, wherein at least one DIMM in said first set of two or more DIMMs comprises a first internal data buffer coupled to said first primary data buffer via said first communication channel;

a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on said mother board, wherein at least one DIMM in said second set of two or more DIMMs comprises a second internal data buffer coupled to said second primary data buffer via said second communication channel; and

a third communication channel electrically coupling said first primary data buffer to said second primary data buffer, and coupling said first primary data buffer and said second primary data buffer to said processor, wherein said first primary data buffer and said second primary data buffer are configured to sample and retransmit data.