IP Library › Granted Patent US 9,673,214
Granted Patent B2
US 9,673,214 · App. 15/071,463 · Granted Jun 6, 2017

Semiconductor device

Inventors: Masaaki Hatano (Yokkaichi, JP); Osamu Matsuura (Kuwana, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H01L27/11582H01L23/528H01L23/53266H01L23/564H01L23/585H01L27/11521H01L27/11526H01L27/11556H01L27/11568H01L27/11573H01L29/0649
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Quick Facts
Patent No.
US 9,673,214
App. No.
15/071,463
Granted
Jun 6, 2017
Kind
B2
Abstract

A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.

Claims (35)

1. A semiconductor device comprising:

an element region disposed on a substrate, semiconductor elements being collocated in the element region; and

a peripheral region disposed on the substrate, the peripheral region surrounding the element region, wherein

the element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate,

the peripheral region includes a peripheral layer arranged to surround the element region,

the peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction,

the first part and the second part have mutually different cross-section structures,

the first part is constituted of a second material having an internal stress with an opposite sign to an internal stress of a first material constituting the wiring layer, and

the second part is constituted of a third material having an internal stress with an identical sign to the internal stress of the first material.

2. The semiconductor device according to claim 1 , wherein

the second part has a larger cross-sectional area in the cross-section structure than the first part.

3. The semiconductor device according to claim 1 , wherein

the second part has a higher arrangement density than the first part.

4. The semiconductor device according to claim 1 , wherein

the third material is a material identical to the first material.

5. The semiconductor device according to claim 1 , wherein

the second material is titanium nitride (TiN) or titanium nitride aluminum (TiAlN).

6. The semiconductor device according to claim 5 , wherein

the first material and the third material are tungsten.

7. The semiconductor device according to claim 1 , wherein

the plurality of wiring layers are collocated on the substrate with interlayer insulating films therebetween.

8. The semiconductor device according to claim 7 , wherein

the second part has a larger cross-sectional area in the cross-section structure than the first part.

9. The semiconductor device according to claim 7 , wherein

the second part has a higher arrangement density than the first part.

10. The semiconductor device according to claim 7 , further comprising:

a memory layer disposed on a side surface of the plurality of wiring layers and the interlayer insulating films, and

a semiconductor layer facing to the plurality of wiring layers across the memory layer.

11. The semiconductor device according to claim 1 , further comprising:

an isolation insulating film disposed on the substrate, wherein

the peripheral layer has a lower end in contact with the isolation insulating film.

12. The semiconductor device according to claim 1 , wherein

the peripheral layer is a guard ring for preventing water from invading from outside.

13. The semiconductor device according to claim 1 , wherein

the peripheral layer is disposed in a dicing region for dicing memory chips.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2016
From: HATANO, MASAAKI; MATSUURA, OSAMU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038289/0039 →
Continuity (2)
Provisional Application 62238384 · Oct 7, 2015
Related Publication 20170103995A1 · Apr 13, 2017