Semiconductor memory device and method of manufacturing the same
View Patent ↗According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer.
1. A semiconductor memory device, comprising:
a plurality of control gate electrodes provided as a stack above a substrate;
a semiconductor layer having as its longitudinal direction a direction crossing the substrate, the semiconductor layer facing the plurality of control gate electrodes; and
a charge accumulation layer positioned between the control gate electrode and the semiconductor layer,
a gap being provided between the semiconductor layer and a lower end portion of the charge accumulation layer.
2. The semiconductor memory device according to claim 1 , further comprising:
a first insulating layer covering a sidewall of the semiconductor layer; and
a second insulating layer covering a sidewall of the charge accumulation layer,
wherein the lower end portion of the charge accumulation layer has a recess portion which is recessed with respect to lower end portions of the first insulating layer and the second insulating layer.
3. The semiconductor memory device according to claim 1 , further comprising
a first insulating layer provided between the semiconductor layer and the charge accumulation layer,
wherein a distance, via the gap, between the semiconductor layer and the lower end portion of the charge accumulation layer, when converted to an electrical resistance value, is not less than a distance equivalent to a film thickness of the first insulating layer.
4. The semiconductor memory device according to claim 1 , wherein
a lower end of the gap is positioned more downwardly than an upper surface of the substrate.
5. The semiconductor memory device according to claim 1 , comprising:
a memory string including a plurality of memory cells connected in series; and
a select gate transistor electrically connected to one end of the memory string,
wherein the plurality of control gate electrodes include:
a first control gate electrode functioning as a control gate electrode of the select gate transistor; and
a second control gate electrode positioned upwardly of the first control gate electrode and functioning as a control gate electrode of the memory cell, and
a lower end of the charge accumulation layer is provided more downwardly than the second control gate electrode.
6. The semiconductor memory device according to claim 5 , wherein
the plurality of control gate electrodes include a plurality of the second control gate electrodes,
and further comprising:
a first inter-layer insulating layer provided between the plurality of second control gate electrodes; and
a second inter-layer insulating layer provided between the first control gate electrode and the second control gate electrode,
wherein the second inter-layer insulating layer has a film thickness larger than that of the first inter-layer insulating layer, and
the lower end of the charge accumulation layer is positioned more downwardly than an upper surface of the second inter-layer insulating layer.
7. The semiconductor memory device according to claim 5 , further comprising
a dummy memory cell provided between the memory cell and the select gate transistor,
wherein the plurality of control gate electrodes include a third control gate electrode positioned between the first control gate electrode and the second control gate electrode, and functioning as a control gate electrode of the dummy memory cell.
8. A semiconductor memory device, comprising:
a plurality of control gate electrodes provided as a stack above a substrate;
a semiconductor layer having as its longitudinal direction a direction crossing the substrate, the semiconductor layer facing the plurality of control gate electrodes;
a first insulating layer covering a side surface of the semiconductor layer;
a charge accumulation layer covering a side surface of the first insulating layer; and
a second insulating layer covering a side surface of the charge accumulation layer,
a lower end portion of the charge accumulation layer having a recess portion which is recessed with respect to lower end portions of the first insulating layer and the second insulating layer.
9. The semiconductor memory device according to claim 8 , wherein
the semiconductor layer and the lower end portion of the charge accumulation layer, when converted to an electrical resistance value, are separated by not less than a distance equivalent to a film thickness of the first insulating layer.
10. The semiconductor memory device according to claim 8 , comprising:
a memory string including a plurality of memory cells connected in series; and
a select gate transistor electrically connected to one end of the memory string,
wherein the plurality of control gate electrodes include:
a first control gate electrode functioning as a control gate electrode of the select gate transistor; and
a second control gate electrode positioned upwardly of the first control gate electrode and functioning as a control gate electrode of the memory cell, and
a lower end of the charge accumulation layer is provided more downwardly than the second control gate electrode.
11. The semiconductor memory device according to claim 10 , wherein
the plurality of control gate electrodes include a plurality of the second control gate electrodes,
and further comprising:
a first inter-layer insulating layer provided between the plurality of second control gate electrodes; and
a second inter-layer insulating layer provided between the first control gate electrode and the second control gate electrode,
wherein the second inter-layer insulating layer has a film thickness larger than that of the first inter-layer insulating layer, and
the lower end of the charge accumulation layer is positioned more downwardly than an upper surface of the second inter-layer insulating layer.
12. The semiconductor memory device according to claim 10 , further comprising
a dummy memory cell provided between the memory cell and the select gate transistor,
wherein the plurality of control gate electrodes include a third control gate electrode positioned between the first control gate electrode and the second control gate electrode, and functioning as a control gate electrode of the dummy memory cell.