Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.
1. A method of operating at least one ferroelectric memory cell, comprising:
biasing a first digit line of a first ferroelectric memory cell to a first voltage;
determining to write a logic value to the first ferroelectric memory cell;
biasing a first cell plate of the first ferroelectric memory cell to a second voltage prior to writing the logic value to the first ferroelectric memory cell, wherein the second voltage comprises a negative voltage, and wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell; and
writing the logic value to the first ferroelectric memory cell.
2. The method of claim 1 , further comprising:
biasing a second cell plate of a second ferroelectric memory cell to the second voltage, wherein biasing the first cell plate to the second voltage is performed in a same operation as biasing the second cell plate of the second ferroelectric memory cell to the second voltage.
3. The method of claim 1 , wherein biasing the first cell plate to the second voltage comprises:
selecting a data storage element corresponding to the first cell plate; and
operating the data storage element after selecting the data storage element, wherein the selecting and the operating of the data storage element temporarily biases the first cell plate to the second voltage.
4. The method of claim 3 , wherein the data storage element comprises at least one latch selected from a group consisting of:
a NAND set-reset latch, a NOR set-reset latch, a JK latch, a D flip-flop, and a T flip-flop.
5. The method of claim 1 , further comprising:
obtaining the negative voltage from a voltage source selected from a group consisting of a negative word line voltage source and a bulk bias voltage source.
6. A method of operating at least one ferroelectric memory cell, comprising:
biasing a first digit line of a first ferroelectric memory cell to a first voltage;
determining to write a logic value to the first ferroelectric memory cell;
biasing a first cell plate of the first ferroelectric memory cell to a second voltage prior to writing the logic value to the first ferroelectric memory cell, wherein biasing the first cell plate to the second voltage comprises biasing the first cell plate to a third voltage between the first voltage and the second voltage and biasing the first cell plate to the second voltage after biasing the first cell plate to the third voltage, wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell; and
writing the logic value to the first ferroelectric memory cell.
7. A method of operating at least one ferroelectric memory cell, comprising:
biasing a first digit line of a first ferroelectric memory cell to a first voltage;
determining to write a logic value to the first ferroelectric memory cell;
biasing a first cell plate of the first ferroelectric memory cell to a second voltage prior to writing the logic value to the first ferroelectric memory cell, wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell;
writing the logic value to the first ferroelectric memory cell; and
biasing a second cell plate of a second ferroelectric memory cell to the second voltage, in parallel with biasing the first cell plate to the second voltage, wherein biasing the first cell plate to the second voltage is performed separately and at a same time as biasing the second cell plate of the second ferroelectric memory cell to the second voltage.
8. A method of operating at least one ferroelectric memory cell, comprising:
biasing a first digit line of a first ferroelectric memory cell to a first voltage;
determining to write a logic value to the first ferroelectric memory cell;
biasing a first cell plate of the first ferroelectric memory cell to a second voltage prior to writing the logic value to the first ferroelectric memory cell, wherein biasing the first cell plate to the second voltage comprises selecting a data storage element corresponding to the first cell plate and operating the data storage element after selecting the data storage element, wherein the selecting and the operating of the data storage element temporarily biases the first cell plate to the second voltage, wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell;
writing the logic value to the first ferroelectric memory cell;
biasing a second digit line of a second ferroelectric memory cell to the first voltage;
determining to write the logic value to the second ferroelectric memory cell;
biasing a second cell plate of the second ferroelectric memory cell to the second voltage prior to writing the logic value to the second ferroelectric memory cell; and
writing the logic value to the second ferroelectric memory cell.
9. The method of claim 8 , further comprising:
activating a set of one or more pass gates coupled to a set of outputs of the data storage element, wherein the activating enables the selecting and the operating of the data storage element to temporarily bias the second cell plate to the second voltage.
10. An electronic memory apparatus, comprising:
a first ferroelectric memory cell comprising a first memory cell selection component coupled to a first terminal of a first ferroelectric capacitor; and
a first cell plate driver operable to switch a second terminal of the first ferroelectric capacitor between a first voltage and a second voltage, wherein the second voltage comprises a negative voltage, and wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell.
11. The electronic memory apparatus of claim 10 , wherein the electronic memory apparatus comprises:
a controller in electronic communication with the first cell plate driver, wherein the controller is operable to control the first cell plate driver to bias a first cell plate of the first ferroelectric memory cell to the second voltage.
12. The electronic memory apparatus of claim 11 , wherein the controller is operable to control the first cell plate driver to:
bias the first cell plate to a third voltage; and
bias the first cell plate to the second voltage after biasing the first cell plate to the third voltage.
13. The electronic memory apparatus of claim 12 , wherein the first cell plate driver comprises at least a first transistor, and wherein the controller is operable to:
switch a source terminal of the first transistor to the third voltage to bias the first cell plate to the third voltage; and
switch the source terminal of the first transistor to the second voltage to bias the first cell plate to the second voltage.
14. The electronic memory apparatus of claim 12 , wherein the first cell plate driver comprises at least a first transistor and a second transistor, and wherein the controller is operable to:
drive a first gate of the first transistor to bias the first cell plate to the third voltage; and
drive a second gate of the second transistor to bias the first cell plate to the second voltage.
15. The electronic memory apparatus of claim 11 , further comprising:
a second ferroelectric memory cell comprising a second memory cell selection component coupled to a first terminal of a second ferroelectric capacitor; and
a second cell plate driver operable to switch a second cell plate of the second ferroelectric capacitor between the first voltage and the second voltage;
wherein the controller is in electronic communication with the second cell plate driver, and wherein the controller is operable to control the first cell plate driver to bias the first cell plate to the second voltage and control the second cell plate driver to bias the second cell plate to the second voltage by applying a same set of one or more signals to the first cell plate driver and the second cell plate driver.
16. The electronic memory apparatus of claim 11 , wherein the first cell plate driver comprises a data storage element, and wherein the controller is operable to:
select the data storage element; and
operate the data storage element after selecting the data storage element, wherein the selecting and the operating of the data storage element temporarily biases the first cell plate to the second voltage.
17. The electronic memory apparatus of claim 16 , wherein the data storage element comprises at least one latch selected from a group consisting of:
a NAND set-reset latch, a NOR set-reset latch, a JK latch, a D flip-flop, and a T flip-flop.
18. The electronic memory apparatus of claim 10 , wherein the negative voltage is obtained from a voltage source selected from a group consisting of a negative word line voltage source and a bulk bias voltage source.
19. An electronic memory apparatus, comprising:
a first ferroelectric memory cell comprising a first memory cell selection component coupled to a first terminal of a first ferroelectric capacitor;
a first cell plate driver operable to switch a second terminal of the first ferroelectric capacitor between a first voltage and a second voltage, wherein the first cell plate driver comprises a data storage element, wherein a magnitude of a difference between the first voltage and the second voltage is greater than a magnitude of a write voltage for the first ferroelectric memory cell;
a controller in electronic communication with the first cell plate driver, wherein the controller is operable to control the first cell plate driver to bias a first cell plate of the first ferroelectric memory cell to the second voltage, and wherein the controller is operable to select the data storage element and operate the data storage element after selecting the data storage element, wherein the selecting and the operating of the data storage element temporarily biases the first cell plate to the second voltage;
a second ferroelectric memory cell comprising a second memory cell selection component coupled to a first terminal of a second ferroelectric capacitor;
a second cell plate driver operable to switch a second cell plate of the second ferroelectric capacitor between the first voltage and the second voltage; and
a set of one or more pass gates operable to couple a set of outputs of the data storage element to a cell plate pulldown mechanism of the second cell plate driver;
wherein the controller is operable to activate the set of one or more pass gates and couple the set of outputs of the data storage element to the cell plate pulldown mechanism of the second cell plate driver, when temporarily biasing the first cell plate to the second voltage, to temporarily bias the second cell plate to the second voltage.