Signed division in memory
Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.
1. An apparatus comprising:
a first group of memory cells coupled to a first access line and a number of sense lines of a memory array;
a second group of memory cells coupled to a second access line and the number of sense lines of the memory array; and
a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations, wherein at least one of the number of operations is performed without activating a column decode line.
2. The apparatus of claim 1 , wherein the controller configured to operate the sensing circuitry to perform a number of operations comprises the controller configured to operate the sensing circuitry to perform a number of AND operations, OR operations, INVERT operations, and SHIFT operations without transferring data via an input/output (IO) line coupled to the column decode line.
3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of transistors on pitch with a number of memory cells and the number of sense lines comprises a number of columns of complementary sense lines that each correspond to a respective memory cell of the first and second groups of memory cells.
4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.
5. The apparatus of claim 4 , wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.
6. A method for performing a signed division operation, comprising:
performing a number of operations on:
a signed dividend element stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and
a signed divisor element stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and
providing a quotient element and a remainder element from dividing the signed dividend element by the signed divisor element;
wherein at least one of the number of operations are performed without activating a column decode line.
7. The method of claim 6 , further comprising performing a second division operation, wherein the signed division operation is a first division operation and the second division operation comprises:
performing a number of second operations on:
a second signed dividend element stored in a third group of memory cells coupled to the first access line and to a second number of sense lines, wherein the signed dividend element is a first signed dividend element;
a second signed divisor element stored in a fourth group of memory cells coupled to the second access line and to the second number of sense lines, wherein the signed divisor element is a first signed divisor element; and
providing a second quotient element and a second remainder element from dividing the second signed dividend element by the second signed divisor element, wherein the quotient element is a first quotient element and the remainder element is a first remainder element;
wherein the first division operation and the second division operation are performed in parallel.
8. The method of claim 7 , wherein the first and the second signed dividend elements are a first and a second signed first values and the first and the second signed divisor elements are a first and a second signed second values.
9. The method of claim 8 , wherein the first signed value is stored in the first and the third group of memory cells as a signed dividend bit-vector and the first and the second signed second values are stored in the second group and the fourth group of memory cells as a signed divisor bit-vector.
10. The method of claim 9 , wherein a number of operations used to perform the first and the second signed division operations in parallel is the same as a number of operations used to perform any one of a plurality of signed division operations.
11. An apparatus comprising:
a first group of memory cells coupled to a first access line and configured to store a plurality of signed dividend elements as bit-vectors;
a second group of memory cells coupled to a second access line and configured to store a plurality of signed divisor elements as bit-vectors; and
a controller configured to operate sensing circuitry to:
perform a plurality of signed division operations by dividing the plurality of signed dividend elements by the plurality of signed divisor elements; and
store results of the plurality of signed division operations in a third group of memory cells without activating a column decode line;
wherein the plurality of signed division operations are performed in parallel.
12. The apparatus of claim 11 , wherein the plurality of results comprise a plurality of bit-vectors that represent at least one of a plurality of quotient elements and a plurality of remainder elements.
13. The apparatus of claim 11 , wherein the third group of memory cells is a same group of memory cells as at least one of:
the first group of memory cells; and
the second group of memory cells.
14. The apparatus of claim 11 , wherein the controller is further configured to operate sensing circuitry to perform each of the plurality of signed division operations on a different element pair including corresponding elements from the plurality of signed dividend elements and the plurality of signed divisor elements.
15. A method for dividing elements comprising:
performing a plurality of signed division operations in parallel on:
a plurality (M) of signed dividend elements stored in a first group of memory cells coupled to a first access line and to a number (X) of sense lines; and
a plurality (M) of signed divisor elements stored in a second group of memory cells coupled to a second access line and to the X sense lines;
wherein the plurality of signed division operations are performed by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without activating a column decode line; and
storing, in parallel and without transferring data via an I/O line, a plurality of results of the signed division operations in:
a third group of memory cells coupled to a third access line and to the X sense lines; and
a fourth group of memory cells coupled to a fourth access line and to the X sense lines.
16. The method of claim 15 , wherein the plurality of results include a plurality (M) of quotient elements stored in the third group of memory cells and a plurality (M) of remainder elements stored in the fourth group of memory cells.
17. The method of claim 16 , wherein each of the M signed dividend elements and the M signed divisor elements are comprised of N bits.
18. The method of claim 17 , wherein each of the N bits in each of the M signed dividend elements and the M signed divisor elements are associated with an index and wherein bits from corresponding elements that are associated with a same index are stored in memory cells that are coupled to a same sense line from the X sense lines.
19. The method of claim 17 , wherein performing the plurality of signed division operations further comprises creating a first signed mask corresponding to the M signed dividend elements that indicate which of the M signed dividend elements have a particular sign.
20. The method of claim 19 , wherein performing the plurality of signed division operations further comprises creating a second signed mask corresponding to the M signed divisor elements that indicates which of the M signed divisor elements have a particular sign.
21. The method of claim 20 , wherein performing the plurality of signed division operations further comprises performing a masked negation on the M signed dividend elements and the M signed divisor elements to result in M negated dividend elements and M negated divisor elements.
22. The method of claim 21 , wherein performing the plurality of signed division operations further comprises performing an unsigned division operation on the M negated dividend elements and the M negated divisor elements.
23. The method of claim 17 , wherein performing the plurality of signed division operations includes performing a number (N) of iterations of operations.
24. The method of claim 23 , wherein each of the N iterations of operations of the unsigned division operation comprises:
using a dynamic mask bit-vector in a number (X) of compute components in the sensing circuitry and in a group of memory cells that store a current dividend bit-vector;
performing a number (P) of iterations of operations comprising:
storing the current dividend bit-vector in the X compute components;
right shifting a bit-vector in the X compute components;
inverting the bit-vector in the X compute components;
performing an OR operation on the bit vector in the X compute components and the static mask bit-vector;
storing the results of the OR operation in the X compute components;
inverting the bit-vector in the X compute components;
performing an OR operation on the bit-vector in the X compute components and the current dividend bit-vector;
storing the bit-vector in the X compute components in the group of memory cells that store the current dividend bit-vector.
25. The method of claim 23 , wherein each of the N iterations of operations of the unsigned division operation comprises:
performing an AND operation on the bit-vector in the X compute components and the dividend bit-vector;
storing the result of the AND operation in the X compute components and the group of memory cells that store the current dividend bit-vector;
right shifting the bit-vector in the X compute components;
performing an OR operation on the bit-vector in the X compute components and on a remainder bit-vector; and
storing the result of the OR operation in the group of memory cells that store the dividend and in a group of memory cells that store the remainder.