Array substrate, display panel, display device and method for driving array substrate

1. A method for driving an array substrate, wherein the array substrate comprises a display region and a non-display region, wherein

the display region is provided with a plurality of data lines and a plurality of scan lines, wherein the plurality of data lines intersects with the plurality of scan lines to define a plurality of pixel units arranged in an array, and each of the plurality of scan lines is electrically connected with a row of the pixel units; and the display region is further provided with N groups of touch electrodes arranged in an array, wherein N is a positive integer larger than or equal to 2; and

the non-display region is provided with a driving circuit, wherein the driving circuit comprises a plurality of clock control switch units, a plurality of shift registers, and a control unit, wherein

the plurality of clock control switch units and the plurality of the scan lines correspond to each other one-to-one,

the plurality of shift registers and the plurality of clock control switch units correspond to each other one-to-one,

control terminal of each of the clock control switch units is connected to the control unit,

an input terminal of each of the clock control switch units is connected to a scan signal outputting terminal of the corresponding shift register, and

an output terminal of each of the clock control switch units is connected to the corresponding scan line; and

the method comprises: in a touch phase, the control unit outputting touch driving signals with inverse polarities to two adjacent groups of the touch electrodes.

2. The method of claim 1 , wherein, in the touch phase, the clock control switch units switch the scan lines corresponding to the clock control switch units into a floating state according to a control signal outputted from the control unit.

3. The method of claim 1 , wherein,

the control unit outputs the touch driving signals with inverse polarities to each group of the touch electrodes in two adjacent touch phases, respectively.

4. The method of claim 1 , wherein the touch phase comprises a first touch sub-phase and a second touch sub-phase, and the control unit outputs the touch driving signals with inverse polarities to each group of the touch electrodes in the first touch sub-phase and the second touch sub-phase, respectively.

5. The method of claim 1 , wherein, each group of the touch electrodes comprises at least one touch electrode, at least one row of the touch electrodes, or at least one column of the touch electrodes.

6. The method of claim 1 , wherein, each of the plurality of shift registers comprises a shift unit and a buffer unit;

wherein an output terminal of the shift unit is electrically connected with an input terminal of the buffer unit, an output terminal of the buffer unit is electrically connected with an input terminal of the clock control switch unit; and

in a display phase, the clock control switch unit transmits a scan signal generated by the shift register to the corresponding scan line, and

in the touch phases, the clock control switch unit switches the corresponding scan line into a floating state.

7. The method of claim 6 , wherein

each of the clock control switch units comprises a transmission gate, a first clock control line and a second clock control line,

an input terminal of the transmission gate is electrically connected to the output terminal of the buffer unit,

the first clock control line is electrically connected to a first control terminal of the transmission gate,

the second clock control line is electrically connected to a second clock control terminal of the transmission gate,

both the first clock control line and the second clock control line are electrically connected to the control unit, and

in the touch phase, the clock control switch unit switches the corresponding scan line to a floating state according to the control signals received through the first clock control line and the second clock control line, and

in the display phase, the clock control switch unit transmits the scan signal generated by the shift register to the corresponding scan line according to the control signals received through the first clock control line and the second clock control line.

8. The method of claim 7 , wherein,

n the display phase, the first clock control line is supplied with the control signal which is a low-level signal, and the second clock control line supplied with the control signal which is a high-level signal;

in the touch phase, the first clock control line is supplied with the control signal which is a high-level signal, and the second clock control line is supplied with the control signal which is a low-level signal.

9. The method of claim 6 , wherein, each of the plurality of clock control switch units comprises a clock inverter, a third clock control line and a fourth clock control line; wherein

an input terminal of the clock inverter is electrically connected with a scan signal outputting terminal of the shift register, the third clock control line is connected to a first control terminal of the clock inverter, the fourth clock control line is connected to a second control terminal of the clock inverter, and both the third clock control line and the fourth clock control line are connected to the control unit.

10. The method of claim 9 , wherein,

in the display phase, the third clock control line is supplied with a control signal which is a low-level signal, and the fourth clock control line is supplied with a control signal which is a high-level signal;

in the touch phase, the third clock control line is supplied with a control signal which is a high-level signal, and the fourth clock control line is supplied with a control signal which is a low-level signal.

11. An array substrate, comprising a display region and a non-display region, wherein the display region is provided with a plurality of data lines and a plurality of scan lines, and the plurality of data lines intersects with the plurality of scan lines to define a plurality of pixel units arranged in an array, wherein each of the plurality of scan lines is electrically connected with one row of pixel units; and the display region is further provided with N groups of touch electrodes arranged in an array, wherein N is a positive integer larger than or equal to 2;

the non-display region is provided with a driving circuit, and the driving circuit comprises:

a plurality of clock control switch units, a plurality of shift registers and a control unit,

wherein the plurality of clock control switch units and the plurality of the scan lines correspond to each other one-to-one, and the plurality of shift registers and the plurality of clock control switch units correspond to each other one-to-one,

an output terminal of each of the clock control switch units is connected to the corresponding scan line, an input terminal of each of the clock control switch units is connected to a scan signal outputting terminal of the corresponding shift register, control terminals of the clock control switch units are connected to the control unit; and

in a touch phase, the control unit is configured to output touch driving signals with inverse polarities to two adjacent groups of the touch electrodes.

12. The array substrate of claim 11 , wherein, in the touch phase, each of the clock control switch units is configured to switch the corresponding scan line to a floating state according to a control signal outputted from the control unit.

13. The array substrate of claim 11 , wherein, the control unit is configured to output the touch driving signals with inverse polarities to each group of the touch electrodes in two adjacent touch phases, respectively.

14. The array substrate of claim 11 , wherein, the touch phase comprises a first touch sub-phase and a second touch sub-phase, and the control unit is configured to output the touch driving signals with inverse polarities to each group of the touch electrodes in the first touch sub-phase and the second touch sub-phase, respectively.

15. The array substrate of claim 11 , wherein, each group of the touch electrodes comprises at least one touch electrode, at least one row of the touch electrodes, or at least one column of the touch electrodes.

16. The array substrate of claim 11 , wherein, each of the plurality of shift registers comprises a shift unit and a buffer unit, and, wherein

an output terminal of the shift unit is electrically connected with an input terminal of the buffer unit,

an output terminal of the buffer unit is electrically connected with an input terminal of the clock control switch unit, and

the clock control switch unit is configured to transmit a scan signal generated by the shift register to the corresponding scan line in a display phase and switches the corresponding scan line to a floating state in the touch phase.

17. The array substrate of claim 16 , wherein, each of the plurality of clock control switch units comprises a transmission gate, a first clock control line and a second clock control line; wherein

an input terminal of the transmission gate is electrically connected to the output terminal of the buffer unit, the first clock control line is electrically connected to a first control terminal of the transmission gate, the second clock control line is electrically connected to a second control terminal of the transmission gate, and both the first clock control line and the second clock control line are electrically connected to the control unit.

18. The array substrate of claim 17 , wherein, the transmission gate comprises a first transistor and a second transistor, wherein a source electrode of the first transistor is electrically connected to a drain electrode of the second transistor and represents an output terminal of the transmission gate; a drain electrode of the first transistor and a source electrode of the second transistor are electrically connected to the output terminal of the buffer unit; a gate electrode of the first transistor is electrically connected to the first clock control line, a gate electrode of the second transistor is electrically to the second clock control line, and the first transistor is a PMOS transistor and the second transistor is a NMOS transistor.

19. The array substrate of claim 16 , wherein, each of the plurality of clock control switch units comprises a clock inverter, a third clock control line and a fourth clock control line; wherein

an input terminal of the clock inverter is electrically connected with the scan signal outputting terminal of the shift register, the third clock control line is connected to a first control terminal of the clock inverter, the fourth clock control line is connected to a second control terminal of the clock inverter, and both the third clock control line and the fourth clock control line are connected to the control unit.

20. The array substrate of claim 19 , wherein, the a clock inverter comprises a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and both the third clock control line and the fourth clock control line are electrically connected to the touch unit;

a drain electrode of the third transistor is electrically connected to a source electrode of the fifth transistor, a source electrode of the third transistor is electrically connected to a drain electrode of the fourth transistor and represents an output terminal of the clock control switch unit, a gate electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor and represents the input terminal of the clock control switch unit, a source electrode of the fourth transistor is electrically connected to a drain electrode of the sixth transistor, a drain electrode of the fifth transistor is electrically connected to a high-level signal line, a gate electrode of the fifth transistor is electrically connected to the third clock control line, a gate electrode of the sixth transistor is electrically connected to the fourth clock control line, a source electrode of the sixth transistor is electrically connected to a low-level signal line, wherein the third transistor and the fifth transistor both are PMOS transistors, and the fourth transistor and the sixth transistor both are NMOS transistors.