Semiconductor memory device having variable resistance elements provided at intersections of wiring lines

1. A semiconductor memory device, comprising:

a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;

a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;

a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines;

a first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to one of the plurality of the second wiring lines, and

a second contact extending in the third direction, one end of the second contact being connected to one of the plurality of the first wiring lines,

the other end of the first contact and a surface intersecting the first direction of the first contact being covered by a first conductive layer, and

the other end of the second contact and a surface intersecting the second direction of the second contact being covered by a second conductive layer.

2. The semiconductor memory device according to claim 1 , wherein

a surface intersecting the second direction of the first contact contacts a first insulating layer.

3. The semiconductor memory device according to claim 1 , wherein

in the first direction, a width of the other end of the first contact is smaller than a width of the one end, and

in the second direction, a width of the other end of the first contact is larger than a width of the one end.

4. The semiconductor memory device according to claim 1 , wherein

the second wiring line and the first contact are formed integrally.

5. The semiconductor memory device according to claim 1 , wherein

a surface intersecting the second direction of the second wiring line and a surface intersecting the second direction of the first contact are formed continuously.

6. The semiconductor memory device according to claim 1 , further comprising

a plurality of the first contacts respectively connected to the plurality of second wiring lines,

wherein the plurality of first contacts are lined up in the second direction with an identical pitch to that of the plurality of second wiring lines.

7. The semiconductor memory device according to claim 1 , wherein

a surface intersecting the first direction of the second contact contacts a second insulating layer.

8. The semiconductor memory device according to claim 1 , further comprising:

a plurality of third wiring lines arranged in the first direction and having the second direction as their longitudinal direction;

a plurality of second variable resistance elements respectively provided at intersections of the second wiring lines and the third wiring lines; and

a third contact extending in the third direction and having one end thereof connected to the third wiring line,

wherein the other end of the third contact and a surface intersecting the second direction of the third contact are covered by a third conductive layer.

9. The semiconductor memory device according to claim 8 , wherein

a surface intersecting the first direction of the third contact is covered by a third insulating layer.

10. A semiconductor memory device, comprising:

a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;

a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;

a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines; and

a first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to the second wiring line,

in the first direction, a width of the other end of the first contact being smaller than a width of the one end, and

in the second direction, a width of the other end of the first contact being larger than a width of the one end.

11. The semiconductor memory device according to claim 10 , wherein

the second wiring line and the first contact are formed integrally.

12. The semiconductor memory device according to claim 10 , wherein

a surface intersecting the second direction of the second wiring line and a surface intersecting the second direction of the first contact are formed continuously.

13. The semiconductor memory device according to claim 10 , further comprising

a plurality of the first contacts respectively connected to the plurality of second wiring lines,

wherein the plurality of first contacts are lined up in the second direction with an identical pitch to that of the plurality of second wiring lines.

14. The semiconductor memory device according to claim 10 , further comprising

a second contact extending in the third direction and having one end thereof connected to the first wiring line,

wherein in the second direction, a width of the other end of the second contact is smaller than a width of the one end, and

in the first direction, a width of the other end of the second contact is larger than a width of the one end.

15. The semiconductor memory device according to claim 10 , further comprising:

a plurality of third wiring lines arranged in the first direction and having the second direction as their longitudinal direction;

a plurality of second variable resistance elements respectively provided at intersections of the second wiring lines and the third wiring lines; and

a third contact extending in the third direction and having one end thereof connected to the third wiring line,

wherein in the second direction, a width of the other end of the third contact is smaller than a width of the one end, and

in the first direction, a width of the other end of the third contact is larger than a width of the one end.

16. A semiconductor memory device, comprising:

a first wiring extending in a first direction;

a second wiring adjacent to the first wiring in a second direction crossing the first direction, the second wiring extending in the first direction;

a third wiring extending in the second direction;

a first variable resistance element provided between the first wiring and the third wiring;

a second variable resistance element provided between the second wiring and the third wiring;

a first contact provided between the first wiring and the second wiring, one end of the first contact being connected to the third wiring, the first contact being extending in a third direction crossing the first and the second directions;

a first conductive layer provided on the other end of the first contact;

a second conductive layer provided on a surface of the first wiring, the first conductive layer and the second conductive layer being at same level; and

a second contact extending in a third direction, the second contact being electrically connected to the first contact through the first conductive layer.

17. The semiconductor memory device according to claim 16 , wherein

the third wiring is integrally provided with the first contact.

18. The semiconductor memory device according to claim 16 , further comprising:

the fourth wiring, the third wiring being provided between the first wiring and the fourth wiring, the fourth wiring extending in the first direction;

the fifth wiring, the third wiring being provided between the second wiring and the fifth wiring, the fifth wiring being adjacent to the fourth wiring in the second direction, the fifth wiring extending in the first direction;

a third variable resistance element provided between the third wiring and the fourth wiring;

a fourth variable resistance element provided between the third wiring and the fifth wiring; and

a third conductive layer provided on the third wiring, the third variable resistance element and the fourth variable resistance element being electrically connected to the third wiring through the third conductive layer.

19. The semiconductor memory device according to claim 18 , further comprising

an insulating film provided above the third wiring, the third wiring being provided between the insulating film and the first contact, and the insulating film being provided between the fourth wiring and the fifth wiring.