Apparatus and methods for debugging on a memory device

1. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and

a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:

store debugging code in the array of memory cells;

execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and

receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is stored within the instructions to perform the logical operations.

2. The apparatus of claim 1 , wherein the array of memory cells are dynamic random access memory (DRAM) cells.

3. The apparatus of claim 2 , wherein the controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to execute the debugging code in the memory device.

4. The apparatus of claim 1 , wherein the controller is configured to receive the instructions pre-resolved by the host.

5. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and

a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:

store microcode instructions containing debugging code in the array of memory cells;

execute microcode instructions to perform logical operations using the sensing circuitry; and

detect one or more bits in the executing microcode instructions to halt a logical operation and perform a debugging routine according to the debugging code on the memory device.

6. The apparatus of claim 5 , wherein:

a bank arbiter is coupled to a plurality of banks in the memory device; and each bank of the plurality of banks includes a memory controller configured to:

receive an instruction block of microcode instructions relevant to a particular bank from the bank arbiter; and

store instructions in the received instruction block to a plurality of locations for the particular bank as allocated by the host.

7. The apparatus of claim 6 , wherein each memory controller is configured to:

receive instructions to start execution of the instruction block;

retrieve instructions from a plurality of locations for a bank of the memory die as needed to handle branches, loops, logical and data operations contained within the instruction block;

cache retrieved instructions local to the bank; and

re-cache retrieved instructions as needed.

8. The apparatus of claim 5 , wherein:

the apparatus further includes logic circuitry coupled to the sensing circuitry, the logic circuitry including latches in the form of sense amplifiers; and

wherein the memory controller is configured to cache and re-cache retrieved instructions to the logic circuitry.

9. The apparatus of claim 5 , wherein:

the apparatus comprises a plurality of memory device, each memory device of the plurality of memory device having a bank arbiter configured to couple to a channel controller via an interface; and

wherein the channel controller is configured to dispatch instruction blocks to each bank arbiter for each of the plurality of memory device.

10. The apparatus of claim 9 , wherein the apparatus is configured to:

receive a subsequent instruction block of microcode instructions to a bank of a respective memory device via a respective bank arbiter;

store instructions in the subsequent received instruction block to a plurality of locations for the bank while the memory controller is executing a previously received instruction block; and

start of future calculations by the compute component.

11. An apparatus, comprising:

a memory device having a bank arbiter coupled to a plurality of memory banks, the bank arbiter to dispatch microcode instructions to the plurality of banks, wherein each bank of the plurality of banks comprises:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations; and

a controller coupled to the array and the sensing circuitry, wherein the controller is configured to:

store debugging code in the array of memory cells;

execute instructions to perform logical operations using the sensing circuitry; and

receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device.

12. The apparatus of claim 11 , wherein the apparatus is configured to:

receive an instruction block of microcode instructions relevant to the bank arbiter from a channel controller; and

store instructions in the received instruction block to a plurality of locations in the array as allocated by the channel controller.

13. The apparatus of claim 12 , wherein:

the array of memory cells is a dynamic random access memory (DRAM) array of memory cells; and

the controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to:

receive the microcode instructions from the channel controller via the bank arbiter; and

route the microcode instructions to the compute component.

14. The apparatus of claim 11 , wherein the controller comprises:

control logic;

a sequencer; and

timing circuitry.

15. The apparatus of claim 11 , wherein the control state machine is configured to:

retrieve the instructions from a dynamic random access memory (DRAM) array on the memory device; and

decode the instructions into microcode operations to be implemented by the sequencer.

16. The apparatus of claim 15 , wherein the sequencer is configured to:

generate sequences of operations for the DRAM array on the memory device, the sequences of operations comprising logical operations using the sensing circuitry; and

wherein the sequences of operations include halting the logical operation and executing the debugging code on the memory device upon receipt of the indication by the sequencer.

17. The apparatus of claim 16 , wherein timing circuitry is configured to provide conflict free access to the DRAM array from a plurality of first in first out (FIFO) queues.

18. The apparatus of claim 17 , wherein the plurality of FIFO queues comprises:

an array computation FIFO;

an instruction fetch FIFO;

a microcode fetch FIFO; and

an array input/output (I/O) FIFO.

19. The apparatus of claim 16 , wherein the control state machine and the sequencer are configured to:

generate status information;

route the status information to the bank arbiter via a status interface; and

wherein the bank arbiter is configured to:

aggregate the status information; and

report the status information to a channel controller via an out of bound bus.

20. A method for debugging on a memory device, comprising:

storing microcode instructions containing debugging code in an array of memory cells;

receiving microcode instructions to a controller on the memory device to perform logical operation;

detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging; and

executing microcode instructions on the memory device using sensing circuitry having a sense amplifier and a compute component to perform the logical operations.

21. The method of claim 20 , wherein the method comprises:

storing the microcode instructions in a dynamic random access memory (DRAM) array of a processing in memory (PIM) device using the controller on the memory device.

22. The method of claim 20 , wherein the method comprises performing a single step debugging operation according to the debug code to step to a next microcode instruction.

23. The method of claim 20 , wherein the method comprises performing a step over debugging operation according to the debug code to step over a next microcode instruction and to continue a perform a debugging routine on a subsequent microcode instruction.

24. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and

a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:

store debugging code in the array of memory cells;

execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and

receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is a bit stored within the instructions to cause the controller to halt the logical operation.

25. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and

a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:

store debugging code in the array of memory cells;

execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and

receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is stored within the instructions to perform the logical operations; and

the indication is configured to cause the controller to;

pause execution of a logical operation; and

continue the logical operation according to the debugging code.

26. The apparatus of claim 25 , wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a debugging step operation.

27. The apparatus of claim 25 , wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a single step debugging operation.

28. The apparatus of claim 25 , wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a step over debugging operation.

29. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and

a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:

store debugging code in the array of memory cells;

execute instructions to perform logical operations using the sensing circuitry; and

receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the instructions are microcode instructions, and wherein the debugging code and the indication are contained in the microcode instructions.

30. A method for debugging on a memory device, comprising:

storing microcode instructions containing debugging code in an array of memory cells;

receiving microcode instructions to a controller on the memory device to perform logical operations,

detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging, wherein detecting the indication in the microcode instructions comprises detecting one or more set bits in the received microcode instructions to halt the logical operation and perform the debugging routine.

31. The method of claim 30 , wherein detecting the one or more set bits comprises:

using a sequencer in the controller to identify a set debug bit in the microcode instructions; and

stopping a program counter and not allowing new instructions to execute.

32. A method for debugging on a memory device, comprising:

storing microcode instructions containing debugging code in an array of memory cells;

receiving microcode instructions to a controller on the memory device to perform logical operations;

detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging; and

setting a debug bit in the microcode instructions programmatically after the microcode instructions are stored on the memory device.

33. A method for debugging on a memory device, comprising:

storing microcode instructions containing debugging code in an array of memory cells;

receiving microcode instructions to a controller on the memory device to perform logical operations,

detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging,

executing microcode instructions on the memory device using sensing circuitry having a sense amplifier and a compute component to perform the logical operations, wherein the executing microcode instructions on the memory device includes executing the microcode instructions on a processing in memory (PIM) device; and

using sensing circuitry on the PIM device to:

perform logical functions including AND, OR, NOT, XOR, NAND, and NOR logical functions; and

non-Boolean logic operations including copy, compare and erase.

34. The method of claim 33 , wherein the method comprises storing the microcode instructions to a plurality of subarrays in a dynamic random access memory (DRAM) on the PIM.